DualSoft tool documents IP, BOPS revs 3-D rendering

DualSoft tool documents IP, BOPS revs 3-D rendering
By Richard Goering, EE Times
March 20, 2000 (10:23 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000320S0008

Startup DualSoft will come to this week's IP2000 Conference with what it says is the first automatic documentation generation utility for Verilog and VHDL designs. HDLDoc reads RTL source files for intellectual-property (IP) blocks and generates HTML or text descriptions of the design.

The product reads and analyzes source code to determine design hierarchy, reset methodology, clocking style, port interfaces and other design-specific attributes. It can infer some functionality from the design alone, and it picks up other cues from comments embedded in the code. It generates what the company describes as a finished, "Web-ready" document that can be given to IP integrators.

"We're automating a task that has been done manually," said Sashi Obilisetty, chief executive officer of DualSoft. "The system integrator can take a look at the document and make a very quick decision about the reusability of IP."

The tool won't replace technica l writers; human beings are still needed to provide a high-level view of the IP. "We're looking at the finished design and trying to generate documentation focused at the designer level," Obilisetty said. "We're automating those things that are routine."

Still, she noted, a user can customize the output to look very much like a polished, human-written document. HDLDoc can be customized with Dualsoft-specific pragmas or comments in source code. Pragmas can also be included to help HDLDoc describe functionality.

A graphical user interface allows customization. The tool offers Verilog-XL-compliant command-line and batch-mode operations. A static expression analysis engine detects and documents parameterizable IP features.

The most common expected use of HDLDoc is in project environments, where IP needs to be documented in some standard way after completion. It can be used for in-house or third-party IP and may also be useful for design services or consulting organizations.

HDLDo c compliance with the documentation standards set forth by the Virtual Socket Interface Alliance and in Motorola's Semiconductor Reuse Standard is "under development," Obilisetty said. DualSoft also plans XML support.

HDLDoc will be available in mid-April starting at $7,500 for a floating license. It runs on all Java-compatible platforms. Further information is at www.dualsoft.com.

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BOPS Inc. announced its family of Mo-Ray scalable floating-point array processor cores at the Game Developers Conference in San Jose, Calif. The family extends the 3-D graphics performance of the BOPS ManArray architecture. BOPS also provided information about the software development kit used to develop applications based on the cores.

The Mo-Ray cores accelerate geometry-processing functions. Their programmable architecture is claimed to accelerate rendering and animation algorithms, allowing for more complicated graphics.

The SDK provides the t ools and libraries needed to develop 3-D graphics geometry algorithms. Further information is available at www.bops.com.