Certus Semiconductor Partners with Pragma Design for Embedded ESD Detection Technology
August 16, 2023 -- Certus Semiconductor is delighted to announce a strategic collaboration with Pragma Design, a distinguished name in innovative electronic design solutions. This partnership marks a significant leap forward in advancing Embedded Electrostatic Discharge (ESD) Detection Technology.
Embedded ESD Detection Technology Overview:
Embedded ESD Detection Technology holds paramount importance in fortifying electronic devices against Electrostatic Discharge, a latent and critical hazard to contemporary electronics. Our collaboration with Pragma Design's ESD Analysis Tool (PEAT) is focused on seamlessly integrating state-of-the-art ESD detection capabilities directly into semiconductor chips. This integration facilitates real-time monitoring and proactive defense against potential ESD incidents, thus safeguarding the integrity of electronic systems.
Wearable devices, especially in the medical field, are particularly vulnerable to ESD events. Now, more than ever, an ESD event can cause life-threatening disruptions in a system. This partnership aims to assist devices (and their wearers) in recovering gracefully from such incidents.
Rationale Behind the Partnership:
Certus Semiconductor is dedicated to innovation and continuous improvement in chip-level IO cell performance. Pragma Design's expertise in system-level design and analysis and their disruptive technological advancement of PEAT technology align perfectly with our goal of helping semiconductor suppliers deliver robust, cost-effective, and high-performance solutions.
Advantages of Embedded ESD Detection:
- Preventive Safeguarding: Real-time monitoring empowers devices to promptly enact protective measures upon detecting an ESD event, mitigating operational disruptions.
- Enhanced Reliability: Implementing embedded ESD detection technology significantly reduces the risk of ESD-induced failures, thereby increasing device reliability and lifespan.
- Real Sustainability: An ESD failure of a 2-cent component triggers downtime and replacement costs. It also results in an often overlooked doubling of the pollution footprint generated by manufacturing and shipping an entire replacement system.
- Economical Viability: By averting ESD-related setbacks, manufacturers can reduce costly warranty claims, mitigate injury risks, and eliminate the need for product recalls.
The Road Ahead:
Pragma and Certus are combining our system-level and chip-level ESD IP and expertise to develop a comprehensive suite of embedded ESD detection solutions. Expect upcoming updates on our progress and breakthrough innovations arising from this synergy.
We are forging a more reliable and sustainable technological future as we adapt this ESD detection technology for real-world production beyond academic exploration.
Related Semiconductor IP
- Stand-Alone ESD Cell in GF 28nm
- Analog I/O Library with a custom 12V ESD Solution IN GF 55nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
- High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
- Full Radiation-Hardened ESD Library in GF 12nm LP/LP+
Related News
- Certus Semiconductor adopts AI-powered Solido to accelerate IO library, analog IP and ESD development
- Certus Semiconductor releases ESD library in GlobalFoundries 12nm Finfet process
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- Rapidus announces collaboration with Siemens for 2nm semiconductor design
Latest News
- SEMI Reports Worldwide Silicon Wafer Shipments Increase 13% Year-on-Year in Q1 2026
- POLYN Technology Announces Tapeout of Automotive Chip
- QuickLogic Establishes New Banking Relationship and Secures $10 Million Revolving Credit Facility
- TES is extending its PMU IP portfolio for X-FAB’s XT018 - 0.18µm BCD-on-SOI technology.
- RF Front-End Modules & Components IP Trends – Q1 2026 Monitoring Release