Best practices for structured-ASIC design

Given the increasing nonrecurring engineering charges and long design schedules associated with deep-submicron standard-cell ASICs, the use of structured ASICs for custom IC design is an increasingly attractive option. Structured ASICs offer good silicon performance at competitive unit cost, with much lower NREs. The wide range of sizes available for the structured ASIC means it can be used either as the main system chip or as a small, cost- effective side chip.

Many physical design issues are already addressed in the structured-ASIC slice design, so the time taken for the back-end layout work can be reduced, leading to quicker signoff and prototype delivery. But the ASIC slices have a predefined structure, so the designer must carefully consider arrangement of chip resources to achieve the desired performance.

FPGAs offer another alternative to ASICs. They are usually based on lookup tables and configurable logic cells, and they are less area-efficient and more power-hungry than comparable ASIC technologies. Once annual production volumes move above 5,000 pieces, it is often much more cost-effective to use a structured ASIC. Still, in many applications, FPGAs serve as an ideal prototyping tool, providing quick turnaround with low up-front cost.

If the design is prototyped in an FPGA, it is important to plan for migration to the chosen structured ASIC. Ideally, co-development using FPGA and ASIC libraries can be done early on. But even without that, a little planning can make the migration fairly painless.

Do

• Employ synthesis tool strategies that avoid mismatches. Typically, designers can use the front-end environment of their choice, taking the design either to vendor netlist or to HDL description at the register-transfer level; but it is likely that there will be different tools, or different versions of the same tool, used for FPGA synthesis and ASIC synthesis. Use a code checker and least-common-denominator coding style to avoid mismatches in results. That will ensure that differing tools don't interpret the RTL code differently.
• Deliver the timing details. The ASIC vendor requires such information to perform synthesis, timing-driven layout and post-layout static timing analysis. Providing good system clock information and an I/O system timing budget, along with any false/multicycle path information on the FPGA synthesis scripts, will speed layout.
• Discuss design-for-test requirements with your ASIC provider early in the program. Although test circuitry does not need to be included in an FPGA prototype, untestable circuitry in an ASIC will lower the fault coverage for the device and may allow faulty parts to pass through the tester. Some ASIC vendors include test insertion and automatic test program generation in their NREs; but dedicated and multiplexed test pins may be required, and extra test circuitry may be needed.
• Add reset and initialization logic. Even though FPGAs don't require it, add reset and initialization logic so that test vectors used on the completed prototypes yield the same result as simulations.
• Decide on a package style and pinout early. Structured-ASIC vendors can provide a wide range of packages that can exactly meet the design requirements, saving cost and board area, but package selection is limited for FPGAs. If pin compatibility with an FPGA prototype is required, discuss the pinout and package selection at an early stage with your ASIC vendor to ensure that it can meet the requirement.

Don't

• Use prototype FPGA RAM features that cannot be matched in the ASIC. Different RAM size may not be a problem since structured ASIC RAMs are usually highly configurable; however, ensure you stay within the overall RAM capacity and number of instances available. Asynchronous access and asymmetric read/write ports with different word widths may not be possible or may require extra wrappers and logic to be added.
• Select FPGA I/O that is not available in the ASIC lineup. Check the ASIC library and match what is available there. This will avoid any surprises when trying to plug your ASIC into your prototype board.
• Use proprietary intellectual property supplied by the FPGA vendors. Try to stick with synthesizable IP, from a reputable vendor, that can be easily used on both the FPGA and the ASIC. Where analog IP such as a phase-locked loop is used, ensure that your target ASIC vendor can match the frequency generation or deskew requirements that the design requires.
• Use long interconnect. Although back-end tools do a good job of reducing interconnect delay by placing connected circuitry close together, in a structured ASIC the RAM positions are fixed, and connecting a RAM on the top of the die with circuitry associated with I/O fixed at the bottom will increase delay. If you have any critical timing interfaces, avoid pinout and RAM assignments that yield a long interconnect after layout.
• Use asynchronous logic, if possible. You may not be able to reproduce an FPGA asynchronous logic path in the structured ASIC.

Frank McMillan (frankm@chipx.com), senior applications engineer at ChipX (Northampton, England)