JPEG Encoder IP Core from CAST gets Rate Control Options, Faster FPGAs
2012-06-04 13:38:00
IP Cores & Design
Semiconductor IP News Archive - Page 971 of 1964
Open-Silicon Announces Industry's First Hybrid Memory Cube Controller IP
2012-06-04 12:03:00
IP Cores & Design
True Circuits Attends Design Automation Conference
2012-06-04 08:05:00
Misc
Calxeda Establishes Subsidiary and Distributor Network In Asia
2012-06-04 06:41:00
Strategic Partnerships
Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard (UCIS)
2012-06-04 05:24:00
EDA & Design Tools
Cadence Collaborates on 3D-IC Design Infrastructure with TSMC
2012-06-04 05:22:00
EDA & Design Tools
DMP and III Collaborate to Promote DMP's Graphics Offering and GPU Integration Services to Taiwanese Customers
2012-06-04 03:48:00
Strategic Partnerships
Atrenta Introduces Fast Lint for SpyGlass
2012-06-04 01:55:00
EDA & Design Tools
Cadence Physical Verification System Qualified for TSMC 28nm, 20nm Process
2012-06-04 01:28:00
EDA & Design Tools
Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20nm Phase I Certification
2012-06-04 01:25:00
EDA & Design Tools
PLDA Announces Live PCI Express Gen3 x8 Demo Running on Xilinx Kintex-7 FPGA
2012-06-01 17:06:00
IP Cores & Design
GLOBALFOUNDRIES Silicon Validates 28nm AMS Production Design; Reveals Digital and AMS Support for Double Patterning at 20nm
2012-06-01 16:57:00
Foundries & Process Nodes
S2C Releases New Prototype Ready ARM11 and ARM9 Modules for FPGA-Based Prototypes
2012-06-01 16:05:00
Misc
Northwest Logic Uses Blue Pearl Software's Analyze to Maximize IP Core Quality
2012-06-01 15:18:00
EDA & Design Tools
Imagination Technologies Group plc: Gilles Delfassy appointed a non-executive director
2012-06-01 15:09:00
People & Leadership
Azini Capital Funds OneSpin Solutions to Accelerate Growth
2012-06-01 14:56:00
Strategic Partnerships
Tiempo, Working with STMicroelectronics, Unveils First 32nm Clockless Test Chip
2012-06-01 14:49:00
SoC Architecture & Assembly
Cavium And Elliptic To Collaborate On Providing Security And Content Protection On Cavium's PureVu Wireless Display SoC
2012-05-31 16:30:00
Commercial Deals
Synopsys Design Implementation Tools Receive TSMC 20nm Phase I Certification
2012-05-31 15:08:00
EDA & Design Tools
APS5 32 bit Microcontroller IP Core for High Performance Embedded ASIC Designs Launched by Cortus
2012-05-31 13:54:00
IP Cores & Design