New Titan IC Systems and Xanadata partnership means huge acceleration to analytics of data in network security solutions
2016-03-01 03:46:00
SoC Architecture & Assembly
Semiconductor IP News Archive - Page 650 of 1948
Express Logic's X-Ware Secure Platform Provides Secure Solution for Information- and Safety-Sensitive IoT Devices
2016-03-01 01:47:00
SoC Architecture & Assembly
Intilop releases Network Security TOE Module for Altera and Xilinx FPGAs for their 10G & 40G Full TCP & UDP Offload Engines
2016-02-29 17:21:00
IP Cores & Design
Hiroshima University Research Team Accelerates Automotive Algorithm Development with Cadence Protium Rapid Prototyping Platform
2016-02-29 17:14:00
EDA & Design Tools
Mentor Graphics Adds Memory Models to Create Industry's First Complete UVM SystemVerilog Verification IP Library
2016-02-29 16:42:00
Verification IP
Rambus Cryptography Research Signs Licensing Agreement with The Athena Group to Accelerate Adoption of DPA Countermeasures
2016-02-29 14:32:00
Strategic Partnerships
Try and adopt MIWOK by Dolphin Integration, a benchmark for Voice Activity Detectors
2016-02-29 14:25:00
Misc
For the 4th quarter of 2015, GPU shipments increased 2.4% from last quarter
2016-02-29 11:59:00
Analysis & Insight
SmartDV Releases Portfolio of Verification Intellectual Properties that Support Platform-independent Simulation Acceleration (SimXL)
2016-02-26 09:00:00
Verification IP
GUC/Partner Jointly Develop USB3.1 PHY/Controller IP
2016-02-26 06:53:00
IP Cores & Design
Arasan announces the Industry's First MIPI DSI-2 Controller IP Cores
2016-02-25 17:16:00
IP Cores & Design
INSIDE Secure announces full year 2015 results along with Company repositioning and restructuring
2016-02-25 13:36:00
Financials
Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
2016-02-24 23:14:00
EDA & Design Tools
Semiconductor Capital Spending Rebound Fails to Materialize in 2015
2016-02-24 16:12:00
Analysis & Insight
Synopsys Accelerates Verification Closure of Multimedia SoCs with Next-Generation Verification IP for HDMI 2.0a and HDCP 2.2
2016-02-24 15:10:00
Verification IP
Allegro DVT Launches AVS2 Compliance Streams
2016-02-24 11:21:00
SoC Architecture & Assembly
Imagination and Mentor Graphics collaborate to speed verification of MIPS-based designs with Veloce and Codelink
2016-02-24 08:43:00
EDA & Design Tools
CEVA Powers DSP Group's Next-Generation Ultra-Low-Power Always-On Voice Processor
2016-02-24 08:35:00
IP Cores & Design
eASIC Enables Improved Real-Time Hardware Acceleration Performance for ASOCS' Fully Virtualized RAN (vRAN) Solution
2016-02-24 05:52:00
Commercial Deals
Credo 100G Retimer Family Delivers Unparalleled Low-Power and Extended Reach
2016-02-24 04:05:00
SoC Architecture & Assembly