See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
2025-05-12 11:22:00
Events & Conferences
Semiconductor IP News Archive - Page 59 of 1948
RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
2025-05-12 10:04:00
Analysis & Insight
Keysom Unveils Keysom Core Explorer V1.0
2025-05-12 09:41:00
IP Cores & Design
Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
2025-05-12 09:04:00
Events & Conferences
PQSecure Partners with Menta to Demonstrate Leakage-Resistant PQC IPs on eFPGA Fabric
2025-05-11 08:26:00
IP Cores & Design
Skymizer Launches HyperThought: Build Your Own AI Chip with Skymizer’s LPU IP
2025-05-09 14:44:00
IP Cores & Design
SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
2025-05-09 10:45:00
SoC Architecture & Assembly
Panmnesia Kicks off $30M Project to Redefine AI Infrastructure with Chiplets, Manycore Architectures, In-Memory Processing, and CXL
2025-05-08 14:07:00
Strategic Partnerships
SEGGER and Quintauris are working together to develop products and technology for the open-source RISC-V ecosystem
2025-05-08 14:02:00
SoC Architecture & Assembly
UMC Reports Sales for April 2025
2025-05-08 09:36:00
Financials
Arm Reports Quarterly Revenue of Over $1 Billion for First Time in Company’s History
2025-05-08 07:05:00
Financials
VESA Releases Compliance Test Specification Model for DisplayPort Automotive Extensions Standard
2025-05-08 06:37:00
Standards & Interconnects
Kyocera Licenses Quadric’s Chimera GPNPU AI Processor IP
2025-05-08 05:44:00
Commercial Deals
Imagination Announces E-Series: A New Era of On-Device AI and Graphics
2025-05-08 05:23:00
IP Cores & Design
Cadence Accelerates Physical AI Applications with Tensilica NeuroEdge 130 AI Co-Processor
2025-05-08 05:10:00
IP Cores & Design
Keysight Expands USB Standards Support in System Designer for USB
2025-05-07 20:54:00
EDA & Design Tools
Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
2025-05-07 20:30:00
Misc
Transforming Chip Design with Agentic AI: Introducing Cadence Cerebrus AI Studio
2025-05-07 20:26:00
EDA & Design Tools
NEO Semiconductor Unveils Breakthrough 1T1C and 3T0C IGZO-Based 3D X-DRAM Technology
2025-05-07 16:36:00
IP Cores & Design
Is the world ready for Platypus, Zero ASIC’s open eFPGA IP? CEO Andreas Olofsson is betting that the answer is “Yes”
2025-05-07 15:24:00
Analysis & Insight