ANSYS And Synopsys To Partner In Accelerating Robust Design Optimization For Next Generation High-Performance Computing, Mobile And Automotive Products
2017-06-19 15:03:00
EDA & Design Tools
Semiconductor IP News Archive - Page 581 of 1964
Truechip Collaborates with OmniPhy for Verification of PCIe Gen4 IP solution
2017-06-19 14:43:00
Strategic Partnerships
Sankalp Semiconductor Announces Availability of 16nm IO Libraries
2017-06-19 14:17:00
IP Cores & Design
Shanghai Frequen Licenses and Deploys CEVA Bluetooth Low Energy IP in New IoT Product Line
2017-06-19 13:14:00
Commercial Deals
Silvaco to Acquire SoC Solutions
2017-06-19 08:51:00
Strategic Partnerships
GUC Successfully Rolls out HBM2 Total Solution
2017-06-19 08:37:00
IP Cores & Design
Truechip Announces First Customer Shipment of Ethernet 400G/200G VIP
2017-06-19 05:47:00
Verification IP
Rambus Launches JEDEC-Standard DDR4 NVRCD for Emerging NVDIMM Applications
2017-06-19 03:18:00
SoC Architecture & Assembly
North American Semiconductor Equipment Industry Posts May 2017 Billings
2017-06-19 03:01:00
Analysis & Insight
Runtime Accelerates Time to Market with New License Allocation Management Solution
2017-06-19 01:26:00
EDA & Design Tools
Barco Silex extends crypto offering with Chacha20/Poly1305 authenticated encryption
2017-06-16 10:07:00
IP Cores & Design
Avery Design Systems Unveils MIPI I3C VIP Targeting Sensors in Smartphone, IoT, Automotive Designs
2017-06-16 09:58:00
Verification IP
The new release of SoC-e IEEE 1588 IP Core supports 10 Gigabit Ethernet
2017-06-16 06:18:00
IP Cores & Design
7 of the Top 10 Smartphone Suppliers Headquartered in China
2017-06-15 15:18:00
Analysis & Insight
Toshiba Selects Synopsys VC Formal Verification Solution
2017-06-15 15:11:00
EDA & Design Tools
Microsemi Announces SoftConsole v5.1, the World's First Freely Available Windows-Hosted Eclipse Integrated Development Environment Supporting RISC-V Open Instruction Set Architecture
2017-06-15 13:44:00
SoC Architecture & Assembly
Avery Design Systems Unveils DDR5 VIP Solution Targeting DDR5 Design Ecosystem
2017-06-15 08:33:00
Verification IP
Noesis Technologies releases its XTS mode AES processor IP Core
2017-06-15 08:01:00
IP Cores & Design
Andes Technology and M31 Technology Collaborated on Optimal Power Efficiency CPU Implementation for IoT SoC Market
2017-06-15 07:02:00
IP Cores & Design
Mentor Verification Is First to Deliver Portable Stimulus Technology Across the Full Enterprise Verification Platform
2017-06-15 05:09:00
EDA & Design Tools