CEA and Siemens collaborate on research to expand applications of Digital Twin for industry
2023-10-03 16:19:00
EDA & Design Tools
Semiconductor IP News Archive - Page 160 of 1957
BrainChip Makes Second-Generation Akida Platform Available to Advance State of Edge AI Solutions
2023-10-03 13:42:00
IP Cores & Design
Tachyum Books Purchase Order to Build System with 25,000x ChatGPT4 Capacity and 25x Faster than Current Supercomputers
2023-10-03 13:38:00
SoC Architecture & Assembly
Semidynamics and SignatureIP create a fully tested RISC-V multi-core environment and CHI interconnect
2023-10-03 08:15:00
IP Cores & Design
Alphawave Semi Earns Great Place to Work® Certification™ for 2023-24
2023-10-02 16:34:00
Misc
Capgemini boosts its semiconductor capabilities in Europe with acquisition of HDL Design House
2023-09-28 16:53:00
Strategic Partnerships
M31 Announces Low-Power IP Solutions for TSMC's N12e Process
2023-09-28 16:47:00
IP Cores & Design
TSMC Announces Breakthrough Set to Redefine the Future of 3D IC
2023-09-28 16:46:00
Foundries & Process Nodes
Keysight, Synopsys, and Ansys Accelerate RFIC Semiconductor Design with New Reference Flow for TSMC's Advanced 4nm RF FinFET Process
2023-09-28 16:46:00
EDA & Design Tools
Percepio Enables Trace Observability for All RTOS, Middleware and Silicon Vendor APIs
2023-09-28 16:46:00
SoC Architecture & Assembly
Intrinsic ID Becomes World's First IP Vendor with PSA Certified Level 3 Root of Trust Component
2023-09-28 16:46:00
IP Cores & Design
How the Worlds of Chiplets and Packaging Intertwine
2023-09-28 16:46:00
Analysis & Insight
China Gears Up for Chip Dumping, Ex-DoC Official Says
2023-09-28 16:46:00
Analysis & Insight
Microchip FPGAs Speed Intelligent Edge Designs and Reduce Development Cost and Risk with Tailored PolarFire® FPGA and SoC Solution Stacks
2023-09-28 16:46:00
SoC Architecture & Assembly
Nanusens technology is key to enabling AI to be smarter
2023-09-28 16:45:00
SoC Architecture & Assembly
Cadence Digital and Custom/Analog Design Flows Achieve the Latest TSMC N2 Certification
2023-09-28 14:52:00
EDA & Design Tools
Cadence Expands Support for 3Dblox 2.0 Standard with New System Prototyping Flows
2023-09-28 13:56:00
EDA & Design Tools
Synopsys and TSMC Streamline Multi-Die System Complexity with Unified Exploration-to-Signoff Platform and Proven UCIe IP on TSMC N3E Process
2023-09-27 15:30:00
IP Cores & Design
Siemens and TSMC collaborate to help mutual customers optimize designs using foundry's newest advancements
2023-09-27 15:11:00
EDA & Design Tools
Chips&Media Announces the Release of "CMNP," the New Neural Processor IP
2023-09-27 09:09:00
IP Cores & Design