The Future of High-Speed SerDes
January 12, 2016
David Axelrad, product marketing manager, SerDes IP, presents Cadence's position prior to the High Speed I/O IP panel discussion at the GSA IP Working Group meeting on Thursday, 22 October, 2015.
You can see his introductory presentation below, where he address major trends in high-speed SerDes:
- Speeds reaching 112Gbps
- Battery life, power consumption scales with data rate
- Consolidation of connectors
Related Semiconductor IP
- SerDes
- 1.25G - 12.5G SERDES
- Multiprotocol SerDes PMA
- SerDes Hard Macro-IP in GlobalFoundries 22FDX
- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
Related Blogs
- Driving the Future of High-Speed Computing with PCIe 7.0 Innovation
- UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC
- Securing the Future of Terabit Ethernet: Introducing the Rambus Multi-Channel Engine MACsec-IP-364 (+363)
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design