The Future of High-Speed SerDes
David Axelrad, product marketing manager, SerDes IP, presents Cadence's position prior to the High Speed I/O IP panel discussion at the GSA IP Working Group meeting on Thursday, 22 October, 2015.
You can see his introductory presentation below, where he address major trends in high-speed SerDes:
- Speeds reaching 112Gbps
- Battery life, power consumption scales with data rate
- Consolidation of connectors
Related Semiconductor IP
- SerDes
- 1.25G - 12.5G SERDES
- Multiprotocol SerDes PMA
- SerDes Hard Macro-IP in GlobalFoundries 22FDX
- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
Related Blogs
- Driving the Future of High-Speed Computing with PCIe 7.0 Innovation
- How Network-on-Chip Architectures Are Powering the Future of Microcontroller Design
- The Future of AI is Modular: Why the SiFive-NVIDIA Milestone Matters
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity
Latest Blogs
- Designing for What Comes Next in AI
- Secure boot on Efinix Titanium Ti60: Getting started with KiviBoot-Tiny
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- World Models at the Edge, in Real Time: V-JEPA 2.1 on the Quadric GPNPU