Memory Standards and the Future
I sat down and talked with Amjad Qureshi recently He is vice president of research and development for the DDR PHY and controller IP. My first assumption, that he joined Cadence with the Denali acquisition, turned out to be wrong. But he does have a 25+ year long history of industry experience in IP, semiconductor, and electronics companies such as Samsung, IBM, Dell, Adaptive Chips, and Cradle Technologies. Most recently he was at ARC, which was acquired by Virage, but he left and joined Cadence before the acquisition of Virage itself. He has been at Cadence for seven years.
To read the full article, click here
Related Semiconductor IP
- DDR Controller IIP
- DDR Memory Controller IP for low power and high reliability
- SDRAM DDR Controller
- DDR Controller supporting DDR5 with Advanced Features Package
- DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
Related Blogs
- Pushing the Boundaries of Memory: What’s New with Weebit and AI
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity
- The Silent Guardian of AI Compute - PUFrt Unifies Hardware Security and Memory Repair to Build the Trust Foundation for AI Factories
- Flash Forward: MRAM and RRAM Bring Embedded Memory and Applications into the Future
Latest Blogs
- From Bug Hunting to Engineering Methodology: Lessons from AI-Driven Development
- Manufacturing Intelligence: Turning EDA Data into Trusted Action
- Execute-in-Place: Getting More from Embedded NVM
- Rethinking RTL flows with AI-driven hybrid formal verification
- Arm and NVIDIA: Building the trusted compute foundation for the agentic AI era