Die-to-Die Interconnect: The UltraLink D2D PHY IP

By Cadence

November 14, 2019

One of the big trends that has been happening somewhat below the radar is the growth of various forms of 3D packaging. I noted this at HOT CHIPS in summer, when a big percentage of the designs were not a single big die, but were multiple die in the same package.

We can argue about the implications of "the end of Moore's Law" but it seems clear that there is no longer a compelling economic reason to put your design into 7nm (and below). If you need the performance, or the lower power, or the density, then go ahead. Until recently, moving a design to the most leading-edge process not only got those things, it also was cheaper per transistor. This meant that there was an economic rationale to keep on the leading edge even if your design performed in the previous-generation node. A competitive dynamic played into this, too—if you didn't move to the advanced node, and your competition did, then you would be at a big cost disadvantage. For years, decades even, the rule of thumb for a process node was that it would roughly double the transistor density, but cost 15% more than the previous node per mm², leaving a cost saving of 35%. But that is no longer true, as you can see from the above graph from Lisa Su's keynote at HOT CHIPS.

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