CEVA creating a wearable IP platform
Processor and GPU cores usually get the limelight, driven by the ARM and Imagination machines occupying the center square of most SoC designs. CEVA has quietly been assembling DSP IP in most of the squares around the edge, and may have just reached critical mass for wearables and IoT devices.
There was plenty of coverage on the recent RivieraWaves acquisition, turning a foothold in Bluetooth into a solid block of squares with world-class Wi-Fi and Bluetooth LE IP. Looking at the CEVA offering now, what they have done with DSP-based IP around the CPU, GPU, camera, and display is impressive
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