Vidatronic Sponsors Design & Reuse's IP SoC Days Conference 2019 in Santa Clara
COLLEGE STATION, TX – April 1, 2019 – Vidatronic, Inc., a leading licensor of power management circuit and CMOS radio frequency (RF) power intellectual property (IP), today announced it is a sponsor of the Design and Reuse (D&R) annual IP SoC Days 2019 Conference (www.design-reuse.com). The conference will be held April 9, 2019 at the Hyatt Regency Santa Clara in Santa Clara, CA. Vidatronic will be in Booth 1 in the mezzanine area of the hotel.
On Tuesday, April 9 at 2:00 PM Vidatronic’s Vice President of Sales and Business Development, Stephen Nolan, will present, Power Management for Internet of Things (IoT) SoC Development, a session designed to help attendees gain a better understanding of how to use power management IP blocks in their IoT SoC designs to differentiate their products and get to market faster.
“This is our first year at the IP SoC Days Conference,” said Stephen Nolan. “We are excited to have this opportunity to show high-level engineers and executives how, by integrating Vidatronic IPs into their SoC designs, they can accelerate their time to market with reduced risk, while seeing significant performance improvements and cost-savings. This year has already been a very exciting year of growth for Vidatronic and we welcome this chance to share our latest IP products in small-process geometries with the IP community.”
“We are delighted to welcome our most valuable IP providers, like Vidatronic, to present their latest innovations at IP SoC Days 19 in Santa Clara. The attention from major semiconductor players this year appears to be excellent,” commented Gabrièle Saucier, CEO of D&R. “This will be an exciting event and definitively proves D&R’s favorite slogan: “IP providers are the innovation seed of the Electronic industry.”
The D&R IP SoC Days Conference is the annual meeting in Silicon Valley for IP providers and IP consumers to share information about technology trends, innovative IP/SoC products, breaking IP/SoC news, IP market evolution, and more. In addition to Vidatronic, D&R welcomes guests and sessions from ARM, Synopsys, Intel, and more.
Additional Information:
Register for the IP SoC Days Conference: https://www.design-reuse.com/ipsocsantaclara2019/registration/
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related News
- Arasan Chip Systems to deliver a keynote at Design & Reuse's IP-SoC Day seminar in Santa Clara
- Open-Silicon to Present on Design-Lite at IP-SOC Days Event in Santa Clara
- Moortec to Showcase its Advances in Embedded PVT Monitoring IP for 40nm-5nm at 2019 TSMC Open Innovation Platform Ecosystem Forum in Santa Clara
- Digital Blocks DB9000 Display Controller IP Core Family Extends Leadership in 8K, Automotive, Medical, Aerospace, and Industrial SoC Designs
Latest News
- Qualitas Semiconductor Secures Strategic IP Licensing Agreement for MIPI Solutions
- Chinese RISC-V Chipmaker SpacemiT Launches K3 AI CPU, Highlighting the Rise of Open-Source Hardware in Intelligent Computing
- Weebit Nano Q2 FY26 Quarterly Activities Report
- Arasan announces the immediate availability of the industries first xSPI NOR + eMMC NAND Combo PHY IP
- AMIQ EDA Gives AI Agents Access to Essential Design and Verification Data