Sidense Introduces Ultra-Low-Power NVM Memory

New one-transistor OTP product targeted for eFuse replacement in precision analog trim applications

Ottawa, Canada – June 7, 2010 – Sidense, a leading developer of Logic Non-Volatile Memory (LNVM) IP cores, today announced the introduction of the Company’s ULP (Ultra-Low Power) one-time programmable (OTP) macro family.  Like all Sidense OTP memory products, ULP macros are based on the Company’s patented one-transistor (1T) split-channel architecture (1T-Fuse™) and require no additional masks or process steps, thus adding no extra wafer processing cost. 

Initially implemented at 180nm, ULP macros are available in configurations from 16 bits to 2 kbits.  The OTP macros feature a low 1.5V read voltage, low power, built-in redundancy and fast startup times, and can be used as field-programmable eFuse replacements.  Multiple analog components on a chip can each use its own ULP macro for trimming or tuning operations.

 “Like all of our NVM products, ULP macros are based on our patented one-transistor bit cell architecture, which enables Sidense to produce secure, reliable and cost-effective field-programmable OTP products,” said Todd Humes, Sidense’s vice president of product engineering.  “ULP was developed for our customers who were looking for an alternative to eFuses for their applications requiring data availability at startup, a very low read voltage, and the flexibility of easy field configuration.”

ULP has already reached TSMC’s Minimum Acceptance Criteria (MAC). The MAC criteria represents the third level of the rigorous and lengthy TSMC IP9000 IP qualification multi-step process and includes the following requirements: a review of the physical design for DRC, LVS, ERC, and Antenna issues; Design for Manufacturability (DFM) compliance; a pre-silicon assessment review of the design for margin and electrical performance; and a silicon assessment and correlation of typical material to demonstrate performance to datasheet specifications over voltage and temperature extremes.

Additional ULP Information

Similar to Sidense’s SLP macro family, designers can use an optional, configurable IPS (Integrated Power Supply) macro with a charge pump for field-programming ULP memory bits.  Sidense customers have already embedded ULP in their products. ULP is currently available in TSMC’s 180nm process and is easily ported to other silicon foundries.

About Sidense

Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield.  The Company’s innovative one-transistor 1T-Fuse™

architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution.  With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.

Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 40nm and is scalable to 28nm and below.  The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs.  Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.  For more information, please visit www.sidense.com.