Optimization key to the future, says EDA pioneer
Dylan McGrath, EE Times
(09/18/2009 7:10 PM EDT)
SAN FRANCISCO—The greatest opportunity for EDA lies in providing optimization for system-on-chip designers as opposed to more functionality, according to a long-standing veteran of EDA.
"EDA as we know it today will be less feature introduction and more about optimization," said Jim Hogan, a 35-year veteran of EDA, IP and the broader semiconductor industry who is currently a managing partner at venture capital firm Vista Ventures LLC. Hogan goes way back in the EDA industry and was an influential executive at Cadence Design Systems Inc. for many years.
To read the full article, click here
Related Semiconductor IP
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
Related News
- ARM And Cadence Establish New Five-Year Agreement Targeting Design Chain Optimization
- CoWare Partners with PowerEscape for Power Optimization Software
- Legend Announces Software Tool for Semiconductor Process Optimization, Verification and Statistical Characterization
- iRoC Technologies Introduces SERPRO Services for Transistor-level Soft Error Rate Analysis and Optimization
Latest News
- Announcing Arm Performix: Empowering developers with scalable performance for the age of AI agents
- MIPI Alliance Launches Physical AI Birds of a Feather (BoF) Group Focused on Humanoids
- Faraday Reports First Quarter 2026 Results
- Cadence Reports First Quarter 2026 Financial Results
- Rambus Reports First Quarter 2026 Financial Results