Synopsys LEDA 3.1 Delivers Full-Chip, Mixed-Language Checking Capabilities and Provides Reuse Guidelines

Prepackaged Rules and Enhanced Configurability Maximize Performance of Synopsys Tools

MOUNTAIN VIEW, Calif., May 14, 2002--Synopsys, Inc. (Nasdaq: SNPS), the technology leader in complex integrated circuit (IC) design, today announced LEDA® 3.1, a programmable coding and design guideline checker that features full-chip, mixed-language checking capabilities to speed development of complex system-on-chip (SoC) designs. LEDA 3.1 adds prepackaged rules that help designers maximize the performance of Synopsys tools such as VCS™, Formality® and Design Compiler™. LEDA 3.1 also enables engineers to check their designs for compliance with reuse guidelines found in the Reuse Methodology Manual (RMM) and the DesignWare® style guide. In addition, it provides enhanced programmability for creating custom coding guidelines.

The popularity of mixed-language design continues to increase, with the code used to describe and verify a complex design often requiring millions of lines. Manually checking this code for errors and style is nearly impossible given today's short design cycles, and LEDA 3.1 addresses this problem by delivering a multi-language capability that can quickly check very large designs coded in both Verilog and VHDL. LEDA 3.1 also identifies and isolates design problems at the chip level, an essential capability to address important issues that may occur across design hierarchy and language boundaries. The addition of reusability guidelines ensures that designers have access to the widely used RMM and DesignWare style guide rules throughout the design cycle.

"At Italtel, we evaluated multiple checkers and chose LEDA because of its superior prepackaged rules as well as its debugging capabilities, "said Gualdi Bruno, senior CAD engineer, research and development at Italtel, a telecommunications network supplier. "LEDA's ability to run chip-level checks and access rules related to Synopsys tools also contributed to our decision. We are very impressed with LEDA's capacity and speed of execution for large designs. The best place to find problems in the design is while we are still writing RTL, and LEDA goes a long way in making this possible."

LEDA 3.1 prepackaged rules greatly enhance a designer's ability to check HDL code for synthesizability, simulatability, testability and reusability. This unique feature provides design guidelines that improve the performance of Synopsys tools. For example, by using the prepackaged VCS rulesets, design engineers can check their code and modify it to achieve greatly improved simulation speeds.

LEDA 3.1 consists of two tools: a LEDA Specifier and a LEDA Checker. The LEDA Specifier is used for creating and compiling custom rules written with a simple command set. The LEDA Checker accepts Verilog and VHDL code, along with compiled rulesets and policies, and outputs error messages indicating lines in the code that violate various rules.

"Our customers need to check large amounts of HDL code for their complex SoC designs," said Mark Warren, technical director, Synopsys Verification Technology Group. "LEDA 3.1 offers capabilities that can handle those large designs and improve performance, testability and reuse. The checker's seamless integration with Synopsys products speeds the design process and ensures high quality results."

Availability
LEDA 3.1 is currently available. Customers with current maintenance agreements will receive Release 3.1 at no additional cost.

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com/.
 

Synopsys, Formality, DesignWare and LEDA are registered trademarks of Synopsys, Inc. VCS, and Design Compiler and DesignWare are trademarks of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.