Synopsys Integrates VERA and VCS to Boost Verification Performance <!-- verification -->

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Nov. 12, 2001-- Synopsys, Inc. (Nasdaq:SNPS - news), the technology leader for complex IC design, today announced the immediate availability of VERA® 5.0. This latest release of VERA is tightly integrated with the VCS(TM) Verilog simulator to provide faster combined run-time performance, real-time access to built-in VCS coverage metrics, and a unified graphical environment for waveform analysis. Along with these performance and productivity enhancing features, this new release of VERA also implements a profiler to help design engineers identify performance bottlenecks and implement higher-speed testbenches.

"We chose Synopsys' VERA 5.0 because of its integrated verification solution," said Wayne Koch, vice president of hardware engineering for Trebia Networks. "We are dedicated to delivering high-performance products that facilitate the design of a new generation of Network Storage systems. VERA 5.0 gives our engineers better performance, access to total coverage and a single waveform debug environment for design and testbench debugging, thus improving our verification quality and productivity."

VERA 5.0 Offers a Fast and Integrated Solution

Overall simulation performance is now improved through a number of optimizations including linking VERA directly to VCS using the VCS Direct Kernel Interface (DKI) instead of traditional slow approaches that deploy the Verilog Programming Language Interface (PLI). Simulations with VERA 5.0 and VCS 6.0.1 now run up to 2X faster compared to previous releases of these tools. VCS DKI is a uniquely optimized direct interface to the VCS simulation kernel that speeds up overall simulation by reducing PLI overhead and enabling VCS simulation optimizations to be applied to the design.

Real-Time Access to VCS' Coverage

In addition to significantly speeding total simulation performance, VERA 5.0 greatly enhances the quality of the overall verification environment by providing real-time access to built-in VCS coverage metrics. This built-in comprehensive capability includes line, toggle and conditional coverage integrated into the high-speed simulation engine. Additionally, VCS' automatic extraction of state machines for state and transition coverage eliminates the need for VERA users to manually define coverage objects. These coverage metrics, coupled with the functional coverage data available in VERA, allow designers to direct their verification efforts to the untested areas of the design, thus eliminating testbench redundancy and improving overall efficiency of the verification environment.

More Performance With the New Profiler

VERA 5.0 offers a new performance profiler that enables design engineers to view the impact of testbench design decisions on simulation performance. The profiler highlights the tasks taking the most simulation time, allowing designers to identify testbench bottlenecks and optimize them to improve overall performance.

"Tellabs relies on leading-edge electronic design tools to help us engineer broadband access systems that meet our customers' needs for converged communications," said Esko Raty, senior manager of ASIC design, Tellabs Oy. "The new VERA 5.0 tool helps us improve productivity and run times to ensure our customers receive equipment that optimizes their network investments."

"Our customers are demanding higher performance and greater integration between our products to keep up with verification of increasingly large designs," said Farhad Hayat, vice president of marketing for the Verification Technology Group at Synopsys. "The unique integration of VERA 5.0 and the latest VCS release significantly empower faster and smarter functional verification."

Complete Functional Verification Solution

Synopsys provides a complete line of integrated functional verification solutions, aimed at achieving the highest functional coverage in the shortest amount of time for complex IC designs. These solutions include Synopsys' VCS(TM) Verilog simulator, Scirocco(TM) VHDL simulator, VCS/Scirocco-MX mixed-HDL simulation, VERA® testbench automation tool, DesignWare® verification IP, LEDA® programmable HDL checker, NanoSim(TM) circuit simulation and Formality® equivalence checker.

Pricing and Availability

VERA 5.0 is available now. VERA Developers License begins at $23,690 for a one-year technology subscription license. VERA Run Time License begins at $5,640 for a one-year technology subscription license. VCS pricing begins at $20,250 for a one-year technology subscription license (TSL).

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS - news), headquartered in Mountain View, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys, VERA, DesignWare, LEDA and Formality are registered trademarks of Synopsys, Inc. VCS, Scirocco and NanoSim are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Synopsys, Inc., Mountain View
     Renae Cunningham, 650/584-1902
     renae@synopsys.com
          or
     Edelman Public Relations
     Sarah Cox, 650/429-2776
     sarah.cox@edelman.com