Latest Synopsys IC Compiler II Release Boosts Quality-of-Results for Performance-Critical Designs

Superior QoR Leads HiSilicon, Movidius to Select IC Compiler II

MOUNTAIN VIEW, Calif. -- May 17, 2016 -- Synopsys, Inc. (Nasdaq:SNPS) today announced the immediate availability of the 2016.03 release of its IC Compiler™ II place-and-route solution, further bolstering its leadership in quality-of-results (QoR) across a diverse application base. Excellent turnaround time (TAT) coupled with achieved-QoR has led customers like HiSilicon and Movidius to select IC Compiler II as their primary implementation tool for their next-generation performance-critical designs. This latest production release raises the bar on achievable QoR through the deployment of new technologies, including congestion-driven restructuring, power-aware concurrent-clock-and-data optimizations, advanced full-flow power optimization and improvements in route-guided design closure. The combination of these capabilities delivers up to 15 percent area, timing and power improvements, enabling the highest levels in performance. With this release of IC Compiler II, Synopsys continues to strengthen its deployment momentum across the broad design community.

The IC Compiler II 16.03 release offers new and powerful technologies enabling superior QoR for complex SoCs while accelerating design closure to meet today's tight time-to-market needs. New QoR-focused optimization technologies include total slack-focused placement and local skew-based clock tree synthesis, which offer significant timing, area and power benefits for all advanced designs. Additionally, specialized techniques such as congestion-driven logic restructuring improve routability and provide additional power savings for datapath-intensive designs. Runtime has been improved in many areas, including 40 percent faster multi-level physical hierarchy capability, enabling designers to seamlessly navigate and manipulate ultra-large chips and blocks to achieve faster closure. Signoff correlation and design convergence has been enhanced with new features including route-guided optimization and PrimeTime® delay calculation within IC Compiler II. For designs at 10 nanometer (nm) and below, the IC Compiler II infrastructure continues to add features including support for lithography-aware placement constraints, fully color-aware routing, as well as advanced timing and extraction modeling. These features are natively captured throughout the infrastructure, enabling a highly convergent physical-design solution capable of achieving high QoR with low runtime.

"Partners like HiSilicon and Movidius have always been at the forefront of innovation," said Antun Domic, executive vice president and general manager of the Design Group at Synopsys. "Their selection of IC Compiler II for performance-critical designs further attests to how the industry-leading QoR IC Compiler II delivers is helping performance-driven customers differentiate themselves. With several key innovative technologies, the latest release of IC Compiler II will further extend these benefits to the larger physical design community designing across both established and emerging nodes."

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 16^th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.