Samsung positions its fab to take on TSMC
EETimes, 2/21/2012 8:03 PM EST
SAN FRANCISCO--Samsung touted its new 32-nm high-k metal gate (HKMG) process at the International Solid-State Circuits Conference here Tuesday (Feb. 21), showing features it hopes might win customers over from a supply constrained TSMC.
While ostensibly presenting its upcoming 32-nm quad-core mobile processor, Samsung spent much of the time presenting its new process, which as well as boasting HKMG, also uses dynamic thermal management and body bias techniques, for a significant 40 percent performance increase over its 45-nm Exynos chip.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
- Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
- 32Gbps SerDes IP in TSMC 12nm FFC
- 32Gbps SerDes IP in TSMC 22nm ULP
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related News
- Synopsys and Samsung Foundry Boost Power, Performance and Area for Modern SoCs on Samsung's SF2 Process
- Siemens extends support for Samsung Foundry's latest process technologies
- Samsung Foundry Certifies Cadence Virtuoso Studio Flow to Automate Analog IP Migration on Advanced Process Technologies
- Cadence Digital and Custom/Analog Design Flows Certified for Samsung Foundry's SF2 and SF3 Process Technologies
Latest News
- Arasan Announces immediate availability of its UFS 5.0 Host controller IP
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
- Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs