Omnitek Releases Highly Optimised 3D LUT IP for FPGAs
BASINGSTOKE, UK -- April 1, 2019 – Omnitek, a world leader in FPGA IP, today announced immediate availability of a unique 3D LUT for colour space conversions and conversion between nonlinear gamuts. This is a critical function in high-demand applications such as Rec. 709/2020 and SDR/HDR conversions, chroma keying and artistic effects such as sepia, black-and-white or vivid colour.
Implemented as IP for FPGAs or programmable SoCs, the 3D LUT makes very efficient use of the resources on these devices to support real-time processing of up to 4K UHD video at 120fps using Lookup Table (LUT) sizes of up to 65x65x65 and a colour depth of up to 16 bits for both input and output. The scalability of the design easily supports alternative configurations including extension to 8K.
Due to the flexibility of the FPGA, the 3D LUT IP can support a variety of different standards, throughput rates and resolutions to suit different application requirements and budgets. Furthermore, with the wide range of additional functions available from Omnitek such as Image Signal Processing, Warp, Blend and Stitch, the 3D LUT can be integrated into a complete system design on an FPGA with connectivity options including HDMI, SDI and V-by-One®.
Roger Fawcett, CEO at Omnitek, commented “We’ve seen a wide range of customer needs for 3D LUTs and are delighted now to be able to offer solutions not only to suit different technical requirements but also different engagement models. Depending on the customer’s level of expertise and resources, we can provide any level of support with the IP, right up to a full chip design or even a board-level design.”
More information is available at www.omnitek.tv/3d_lut_datasheet .
Related Semiconductor IP
- High-performance and low-power 3D graphics IP core
- RISC-V GPGPU for 3D graphics and AI at the edge
- 3D, motion adaptive, video noise reduction IP core
- High quality video decoder IP Core with 3D comb filter and supporting fixed rate sampling
- AI-Capable 3D GPU
Related News
- System-level UCIe IP for early architecture analysis of 3D Chiplet Design and Packaging
- Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
- Silicon-Proven 14-Bit 4.32 GSps Wide Band ADC IP Core with Time-Interleaved Pipeline Architecture Now Available for Whitebox Licensing with No Royalty Fees
- T2M-IP Unveils MIPI D-PHY v2.5 Tx and DSI Tx Controller v1.2: Silicon-Proven, Low-Power, Cost-Effective IP Core Solutions for Advanced SoCs
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers