XYALIS Brings Cost Reduction To Mask Design
GRENOBLE, France, May 27, 2010 -- As technology progresses the cost of a complete mask set has been increasing. It is not rare to see a complete mask set reach millions of dollars with the newest technology nodes, a significant part of the overall project cost. It is then critical for design teams, mask data preparation teams, and mask shops to implement a robust Mask Data Preparation flow, which not only increases the productivity of the mask set creation, but also removes any risk of error during the work intensive process.
Over the last few years, XYALIS has been developing Mask Data Preparation tools in close collaboration with leading semiconductor and mask companies. This year at the Design Automation Conference XYALIS announces two new modules, to complete its proven fully integrated Mask Data Preparation solution.
XYALIS introduces an automated mask set generation tool, which supports today’s most advanced technologies. In a few minutes design teams create complex mask sets from reusable process requirements. The tool simplifies the creation of Multi-Layer Reticules and Multi-Framing Masks that have become more prevalent over the years in order to reduce cost. It fully automates the flow for magnified masks, 1X masks, backside masks, and heterogeneous, multi-chips masks, and warrants that all the masks of a complex mask set meant for diverse equipments are fully compatible. The result is a streamlined mask creation process in a portion of the time with no error due to manual intervention.
As Multi-Project Wafers (MPWs) or shuttles are becoming more common for prototypes, and low production chips, XYALIS enhances its long proven MPW generation solution with the release of a production aware placement engine, which takes into account production requirements (manufacturing costs, expected production volumes, and packaging information) to generate the most cost-effective assembly placement. This placement engine is fully integrated in the intuitive MPW development environment.
These two new modules complete XYALIS Mask Data Preparation solution, which also includes the most user-friendly automatic Frame Generation solution on the market. This solution uses intuitive re-usable process templates to automate the insertion of manufacturing items into frames, cutting time to manufacturing, avoiding costly errors, and minimizing the scribe width for optimum silicon usage.
XYALIS Mask Data Preparation suite is fully integrated in order to deliver a robust and automated solution, which slashes the time to mask creation and eliminates the risk of errors common to the otherwise manual approach. For more information come and see XYALIS at the Design Automation Conference, June 14-16, in Anaheim California (Booth 162).
ABOUT XYALIS
Established in 1998, XYALIS is headquartered in Grenoble, and is now the leading specialist in layout finishing and GDSII/OASIS processing software. Designed to solve problems which the major ECAD companies do not address, the range consists of GTstyle, GTmuch, GTframe, GTviewer, GTcheck, GTreplace, GTpickcell and GTlayer. Conversion tools which translate GDSII to OASIS (and vice versa) are also available. Risc/UNIX systems are either Sun Solaris or HP-UX workstations or Linux.
Related Semiconductor IP
- Motorola MC6845 Functional Equivalent CRT Controller
- Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
- Display Controller – LCD / OLED Panels (Avalon Bus)
- High-Performance Memory Expansion IP for AI Accelerators
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
Related News
- Altera Showcases Productivity and Cost Reduction Solutions for Multichannel Systems at 2012 NAB
- Consumer Electronics Application Processor Hits the Performance Cost Reduction Sweet Spot
- Accusonus Achieves 60 Percent Reduction in Computational Cost of Speech Enhancement Software for Cadence Tensilica HiFi DSPs
- Real Wireless Research Shows One Third Reduction for Private Network Infrastructure Cost Using AccelerComm 5G physical layer IP solution
Latest News
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- Intel’s Altera Unit Nears Sale as Silver Lake Reportedly Leads Talks
- Cadence Reports Fourth Quarter and Fiscal Year 2024 Financial Results