LogicVision calls on 'ET' 4.0 to lower test costs for SoCs

LogicVision calls on 'ET' 4.0 to lower test costs for SoCs
By Semiconductor Business News
February 25, 2002 (12:26 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020225S0042

SAN JOSE -- LogicVision Inc. here today announced a new embedded software and hardware solution said to reduce the cost of test for system-on-a-chip (SoC) and other complex ICs.

The product, dubbed Embedded Test 4.0 (ET 4.0), reduces silicon debug and diagnostics time in chip designs, thereby extending the life of existing automatic test equipment (ATE) or enabling the use of lower cost testers, according to San Jose-based LogicVision.

ET 4.0 streamlines the process of architecting, implementing, and integrating an embedded test solution. It is also said to be the world's first product that enables a chip designer to design hierarchical test capability and seamlessly reuse it for silicon debug and manufacturing test.

In addition, ET 4.0 introduces a vector-less transfer of test data, and provides an ATE independent interactive user interface that enables real-time hierarchical diagnostics for logic, memory and phase-lock loops.

"This is the first known solution to successfully bridge the disciplines of IC design, IC diagnostics and characterization, and IC manufacturing test to create a seamless flow to system test," said Vinod Agarwal, LogicVision's president and CEO. "We believe LogicVision's Embedded Test 4.0 will help ensure accurate, highly efficient and cost-effective testing of complex SoCs, benefiting the entire semiconductor industry," he said.

ET 4.0 enables automated test generation in chip designs. The product's so-called IC Debug feature enables debugging directly on the tester and provides full access and control of all embedded test controllers within the chip under test.

It also includes a LogicVision Database (LVDB) that generates manufacturing-ready test databases. LVDB collects all the necessary information to describe generated and contained embedded test IP for the SoC. This capability enables both vector-less hand-off from design to manufacturing and on-the-fly pattern generation at the tester.

ET 4.0 is now available for Solaris and HP-UX operating system.