New Package Option for Lattice MachXO PLD Family Reduces Cost and Board Area
HILLSBORO, OR - JUNE 29, 2009
- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of a new 0.8-mm pitch 256-pin Chip-Array BGA (caBGA256) package for its popular MachXO™ PLD family that provides designers with a broader range of package options for implementing cost-sensitive, board space constrained designs. The Mach XO640, XO1200 and XO2280 devices are now available in the 14 x 14 mm, caBGA256 package with up to 211 user I/O. The new packages provide designers with 10% lower cost and 30% reduction in board area than previously available on 1.0-mm pitch 256-pin Fine-Pitch Thin BGA (ftBGA256) packages.
"Many of our customers who use MachXO devices in telecom infrastructure, server, industrial and consumer applications are increasingly adopting 0.8-mm pitch package technology," said Chris Fanning, Lattice Corporate Vice President and General Manager of Low-Density and Mixed Signal Solutions. "The addition of the caBGA256 package to the MachXO PLD family provides designers with reduced cost and board area optimization options that are critical in high volume cost-sensitive applications."
Ideal for general purpose I/O expansion, control, bus bridging and power-up management functions in a wide range of low-density applications, the instant-on, easy-to-use MachXO PLD family offers users the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance, flexible multi-voltage I/O, small footprint, remote field upgrade (TransFR™) technology and low power sleep mode, all in a single device.
"We use MachXO PLDs in our Single Board Computer (SBC) product, which is used in a broad range of industrial applications. The MachXO PLDs give us the instant-on, flexible user I/O and single chip solution we need," said Arun Kumar, Project Lead at Mistral Solutions. "The new caBGA256 package on three different MachXO logic densities provides us with a wider range of package choices and the migration flexibility to implement our board area constrained designs at a lower price."
Pricing and Availability
Production devices of the Mach XO640, XO1200 and XO2280 in the caBGA256 package are available now. Volume pricing for the Mach XO640 caBGA256 is $2.75 in 250,000 unit volumes.
Software Support
The new MachXO640, XO1200 and XO2280 caBGA256 device packages are supported in Lattice's ispLEVER® version 7.2, Service Pack 2 software. The free ispLEVER Starter software can be downloaded from the Lattice website at www.latticesemi.com/products/designsoftware/isplever/ispleverstarter
About MachXO PLDs
The MachXO family of non-volatile, infinitely reconfigurable PLD devices is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Combining an optimized look-up table (LUT) architecture with low-cost embedded Flash process technology, the instant-on, easy-to-use MachXO devices are the most versatile, non-volatile PLDs for low-density applications. Available in commercial, industrial and automotive grades, the MachXO PLDs offer 256 to 2280 look-up tables (LUTs), up to 271 user I/O and are supported in thin quad flatpack (TQFP), chip-scale BGA (csBGA), chip-array BGA (caBGA) and fine-pitch thin BGA (ftBGA) packages from 100 to 324 leads. The MachXO PLDs offer a range of power supply options from 3.3V, 2.5V, 1.8V and 1.2V and can also be run off a single 3.3V core supply. For more information about the Lattice MachXO PLD family, visit www.latticesemi.com/products/cpldspld/machxo
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD and Mixed Signal programmable logic solutions. For more information, visit www.latticesemi.com
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- Industry-Leading Lattice MachXO2 PLD Family Now Available In Small WLCSP Package
- Lattice MachXO2 PLD Family Sets New Standards for Low Cost, Low Power Designs
- Lattice Semiconductor and System General Announce Programming Support for Lattice MachXO2 PLD Family
- Lattice Announces New 32 QFN Package For MachXO2 Programmable Logic Devices
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology