IP core handles soft errors
IP core handles soft errors
By Chris Edwards, EE Times UK
December 1, 2000 (8:34 a.m. EST)
URL: http://www.eetimes.com/story/OEG20001201S0015
Iroc Technologies has developed what it reckons is the first intellectual property (IP) core to handle soft errors caused by alpha radiation. Based on the Sparc version 8 architecture, the IP contains protection elements for memory cells and logic. The core has been put into a test chip made by STMicroelectronics on a 0.25µm. It runs at up to 100MHz. Dr Michael Nicolaidis, Iroc's chief technical officer, says the core has more than 98% soft error coverage and is cheaper to implement than designs based on traditional techniques that depend on duplicate processing elements. Eric Dupont, CEO, added: "In developing this processor using a commercial standard-cell library, we have proven that our methodology is the first cost-effective solution to deal with the soft errors issue in commodity systems."
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
Related News
- iRoC launches radiation test shuttle service for soft errors
- Soft errors become hard truth for logic
- DIAMOND Project to Provide Integrated Diagnosis and Correction for Spec, Design and Soft Errors
- Logic Design Solutions launches an EXFAT IP Soft Core for NVMe Host
Latest News
- SEALSQ and IC’Alps Unify Expertise to Deliver Integrated Post-Quantum Cybersecurity and Functional Safety for Autonomous Vehicles
- PUFsecurity’s PUFrt Anchors the Security of Silicon Labs’ SoC to Achieve the Industry’s First PSA Certified Level 4
- The next RISC-V processor frontier: AI
- PQShield joins EU-funded FORTRESS Project: Pioneering Quantum-Safe Secure Boot for Europe’s Digital Future
- PQSecure Achieves NIST CAVP Validation