InPsytech showcases 3nm UCIe 3.0 technology at OCP 2025, Accelerating Innovation in Chiplet Ecosystem
TAIPEI, Oct. 13, 2025 -- InPsytech, a subsidiary of Egis Technology (6462.TWO) specializing in high-speed interface intellectual property (IP) development, announced today that it will participate in the Open Compute Project (OCP) Global Summit 2025, to be held in San Jose, California, from October 13–16, 2025. At the event, InPsytech will showcase its latest 3nm UCIe high-speed interface technology demo, featuring support for the newest UCIe 3.0 standard, 3D packaging integration, and ultra-high-speed, low-power performance. This demonstration highlights InPsytech's advanced R&D capabilities in Chiplet interconnect technology and its role in supporting Egis Group's broader strategy in semiconductor design and heterogeneous integration.
Industry-Leading 3nm 64G UCIe Technology — High Speed, Low Power, Full UCIe 3.0 Support
InPsytech has long focused on high-speed and low-power interface IP technologies. Its UCIe (Universal Chiplet Interconnect Express) portfolio supports advanced process nodes from 22nm down to 2nm, optimized for 3nm production. The IP achieves data transfer rates up to 64 GT/s, while supporting 2.5D and 3D packaging architectures to enable high-efficiency chip-to-chip interconnects and heterogeneous integration. The showcased 3nm UCIe 3.0 demo fully complies with the latest UCIe 3.0 specification, demonstrating InPsytech's leadership in next-generation process technology and Chiplet ecosystem development.
Collaborating with Alcor Micro to Advance the Arm Chiplet Ecosystem
InPsytech's UCIe technology has been successfully adopted in Alcor Micro Corp.'s latest Arm-based CPU platform Mobius100 (CSS V3), which will also be featured at the OCP 2025 Summit. The platform is built on Arm Neoverse CSS architecture, supporting CPU die-to-die interconnects and flexible integration with GPUs, NPUs, and various AI accelerators — driving advancements in heterogeneous computing and Chiplet design. Both InPsytech and Alcor Micro are members of the Arm Total Design (ATD) program, jointly fostering collaboration and innovation across the Arm Chiplet ecosystem.
"We are proud to demonstrate our leadership in this field alongside Alcor Micro," said David Hsu, COO of InPsytech. "We have strong confidence in the future of UCIe within the Arm Chiplet ecosystem and believe that InPsytech's UCIe technology will accelerate Chiplet adoption, bringing new innovation and breakthroughs to the global semiconductor industry."
Exhibition Details
Event: OCP Global Summit 2025
Date: October 13–16, 2025
Location: San Jose Convention Center, California, USA
Exhibit Zone: Innovation Village Zone
Showcase: 3nm UCIe 3.0 Demo (with 3D Package Support)
Partner: Alcor Micro Corp.
Related Semiconductor IP
- UCIe-A PHY and Controller
- UCIe-S PHY and Controller
- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
- UCIe D2D Adapter
- UCIe Die-to-Die Chiplet Controller
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