FinFETs Not the Best Silicon Road
Handel Jones, International Business Strategies Inc.
EETimes (3/27/2014 05:05 PM EDT)
Specifically, next-generation 20nm bulk high-K metal gate CMOS and 16/14nm FinFET process will deliver smaller transistors. However, they will also have a higher cost per gate than today's 28nm bulk HKMG CMOS.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related News
- Law firm urges Supreme Court to decide Rambus vs. Infineon
- The Great Debate: SOC vs. SIP
- Process vs. density in DRAMs
- Balancing cost vs. security for embedded design
Latest News
- Silicon Creations Celebrates 20 Years of Global Growth and Leadership in 2nm IP Solutions
- TSMC Debuts A13 Technology at 2026 North America Technology Symposium
- Cadence Collaborates with TSMC to Accelerate Design of Next-Generation AI Silicon
- Synopsys Partners with TSMC to Power Next-Generation AI Systems with Silicon Proven IP and Certified EDA Flows
- JEDEC® Previews LPDDR6 Roadmap Expanding LPDDR into Data Centers and Processing-in-Memory