embedded world 2024: Codasip demonstrates CHERI memory protection
Munich, Germany -- March 14, 2024 –Codasip, the leader in RISC-V Custom Compute, will demonstrate CHERI memory protection and HW/SW co-optimization at next month’s embedded world 2024 in Nuremberg, Germany. The technologies are enabled by Codasip’s unique Custom Compute offering combining the Codasip Studio design automation tools with a range of customizable RISC-V processor IP.
Codasip will showcase its Custom Compute offering in hall 4, stand 4-368. Visitors will get to see fine-grained memory protection with CHERI. This technology, invented at Cambridge University and brought to commercial implementations by Codasip, actively prevents the most common cyberattacks with the potential of eliminating approximately 70 percent of vulnerabilities documented in the Common Vulnerabilities and Exposures (CVE) program. As announced in October 2023, Codasip is adding built-in fine-grained memory protection to its recently launched 700 processor family by extending the RISC-V ISA with CHERI-based custom instructions.
In addition, the company will show how to profile an embedded application to identify bottlenecks in the code and how custom instructions can be easily added to optimize the hardware to improve the application’s performance. Examples of the potential gains from HW/SW co-optimization include:
- 2x performance gain running the SHA512 cryptographic hash algorithm
- 2.5x speedup and 30% reduction in power consumption for AI/ML workloads
As part of the embedded world conference program, Codasip’s CTO Zdenek Prikryl will present the session “Customized RISC-V in a simple game console” (Session 8.5 SYSTEM-ON-CHIP (SoC) DESIGN / RISC-V 2) on Thursday 11 April.
Anyone interested in learning more about Codasip’s offering can request a meeting at codasip.com/events/embedded-world-2024/
The embedded world exhibition and conference is the world’s leading meeting place for the embedded community. Taking place in Nuremberg, Germany on April 9-11, the conference gathers leading experts, key players, and industry associations from the global embedded community. The conference is focused on the world of embedded systems, from components and modules to operating systems, hardware and software design, M2M communication, services, and various issues related to complex system design.
Don’t miss Codasip at #ew24.
Related Semiconductor IP
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
Related News
- Codasip L31 customizable RISC-V core is an Embedded World Best in Show
- embedded world 2023: Codasip presents on custom compute and RISC-V design
- Think Silicon to Showcase its Latest Ultra-Low-Power 3D Graphics and AI in One IP Architecture at Embedded World 2024
- VeriSilicon showcased its latest power-efficient IP applications at Embedded World 2024
Latest News
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- Intel’s Altera Unit Nears Sale as Silver Lake Reportedly Leads Talks
- Cadence Reports Fourth Quarter and Fiscal Year 2024 Financial Results