Credo First to Publicly Demonstrate 112G SerDes in 7nm at TSMC's 2018 China OIP Forum
San Jose, California, Oct 30th, 2018 – Credo, a global innovation leader in high performance, low power connectivity solutions for 100G, 200G, and 400G port enabled networks, today announced it will demonstrate its advanced high performance, low power, mixed-signal 112Gbps PAM4 SerDes developed in TSMC’s 7nm process technology node at this week’s TSMC 2018 Open Innovation Platform (OIP) Ecosystem Forum in Nanjing, China.
“We are proud to be on the world stage with our partner TSMC showcasing 112G SerDes in TSMC’s advanced 7nm node,” said Jeff Twombly, vice president of marketing and business development of Credo. “End-to-end 112Gbps per lane connections are key to enabling the industry to rapidly build out the next-generation 100G, 400G and 800G Ethernet cloud networks and now merchant silicon providers and system ASIC developers have clear path forward to deliver the required higher bandwidth solutions at lower power and optimum lane count configurations.”
In 2016 Credo demonstrated its unique mixed-signal 112G PAM4 SerDes technology in 28nm to enable low power 100G per lambda optical modules and then quickly migrated the architecture to 16nm to deliver innovative, complementary 112G electrical connectivity solutions. This third port of Credo’s silicon hardened 112G SerDes architecture to 7nm now allows SoC developments to confidently embrace TSMC advanced 7nm processing node.
WHERE: Fairmont Nanjing; TSMC OIP Ecosystem Forum
DEMOS: Credo Booth #23
WHEN: Tuesday, October 30th, 2018; Expo Floor Hours: 9:30am to 5:15pm
WHAT: The TSMC OIP Ecosystem Forum brings together TSMC's design ecosystem companies and TSMC customers to share practical, tested solutions to today's design challenges. Success stories that illustrate TSMC's design ecosystem best practices highlight the event.
About Credo
Credo is a leading provider of high performance, mixed-signal semiconductor solutions for the data center, enterprise networking and high-performance computing markets. Credo's advanced Serializer-Deserializer (SerDes) technology delivers the bandwidth scalability and end-to-end signal integrity for next generation platforms requiring single-lane 25G, 50G, and 100G connectivity. Credo makes its SerDes available in the form of Intellectual Property (IP) licensing on the most advanced process nodes and with complementary product families focused on extending reach and multiplexing to higher data rates. Credo has offices in San Jose, Taiwan, Shanghai and Hong Kong.
For more information: www.credosemi.com
Related Semiconductor IP
Related News
- Credo First to Demonstrate 7nm, 112G XSR SerDes
- Credo Launches 112G PAM4 SerDes IP for TSMC N3 Process Technology
- Credo Demonstrates Single-Lane 112G and 56G PAM-4 SerDes IP at TSMC OIP Forum
- Credo Demonstrates 112G PAM4 SR, 56G PAM4 LR, and 56G NRZ SerDes Technology at DesignCon
Latest News
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Arm Announces Appointment of Eric Hayes as Executive Vice President, Operations