Conexant chairman: Fabless IC designers face rising design costs
by LR Huang, Shanghai; Adam Hwang, DigiTimes.com
The biggest challenge fabless IC design houses face in the future will be the increasing cost of IC design, indicated Conexant Systems chairman and Fabless Semiconductor Association (FSA) vice chairman Dwight Decker, at the IC Industry Development Forum held on April 22 in Shanghai, China.
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- Fabless firms outpace IDMs in costs, gross margins
- ICC Offers Java-Optimized ARM Processor-Based Platform To Fabless Consumer Electronics Designers
- Certicom Launches New Product for Fabless Semiconductor Designers to Prevent Gray Market Chip Theft
- Broadcom sees rising 20 nm costs amid handset push
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology