Conexant chairman: Fabless IC designers face rising design costs
by LR Huang, Shanghai; Adam Hwang, DigiTimes.com
The biggest challenge fabless IC design houses face in the future will be the increasing cost of IC design, indicated Conexant Systems chairman and Fabless Semiconductor Association (FSA) vice chairman Dwight Decker, at the IC Industry Development Forum held on April 22 in Shanghai, China.
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
Related News
- Fabless firms outpace IDMs in costs, gross margins
- ICC Offers Java-Optimized ARM Processor-Based Platform To Fabless Consumer Electronics Designers
- Certicom Launches New Product for Fabless Semiconductor Designers to Prevent Gray Market Chip Theft
- Broadcom sees rising 20 nm costs amid handset push
Latest News
- EU DARE Project Is Scrambling to Replace Codasip
- Sofics and Alcyon Photonics Partner to Support Next-Generation Photonic Systems
- QuickLogic Appoints Quantum Leap Solutions as Authorized Sales Representative
- Cadence and NVIDIA Expand Partnership to Reinvent Engineering for the Age of AI and Accelerated Computing
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud