Cebatech Announces GZIP Family of CebaIP Cores for Efficient High Speed Compression and Decompression inside Data and Storage Networking ASICs and FPGAs

Easy-to-integrate cores provide new levels of integration and performance for hardware compression and decompression

EATONTOWN, NJ. – May 15, 2007 – CebaTech Inc., an innovative intellectual property (IP) developer using state of the art in-house electronic system level (ESL) development tools, today announced the availability of the GZIP family of CebaIP Cores™. The GZIP family provides comprehensive, standards-based, lossless data compression for use in storage and data networking ASICs and FPGAs. Integrating the GZIP family of IP cores onto storage and data networking integrated circuits (ICs) can greatly reduce the operational costs of storing and transmitting data by end users of these ICs. Designers can choose from a number of available configurations to meet their desired speed, compression efficiency, and area requirements.

The GZIP family of cores is based on CebaTech’s integrated CebaIP Platform™ . The CebaIP platform provides a modular approach to offering IP cores, enabling design engineers to quickly and easily integrate each configuration into their ASICs or FPGAs.

Using the CebaIP Platform’s integrated advanced direct memory access (DMA) controller with the OpenBSD software driver, designers are able to rapidly achieve complete compression, decompression, and encryption offload solutions.

The GZIP family is standards-based and conforms to the popular “deflate” standard as specified in RFC1951. File formats for both ZLIB and GZIP, as specified in RFC1950 and 1952, are also supported. Data rates range from 2Gb/s and scale to 8Gb/s while typical compression ratios for benchmark files sets are in the range of 2.5:1 to 3.5:1.

The GZIP family also includes optional advanced encryption standard (AES) capability with select cipher modes for securing “data at rest” inside the enterprise. AES data rates range from 3Gb/s and scale to 12Gb/s. Supported cipher modes include ECB, CBC, GCM, and XTS with keys sizes of 128b, 192b, and 512b. (XTS is the latest recommendation by the IEEE in the P1619 standard for encryption of storage devices.)

“With the exponential growth of stored data inside the enterprise, the desire to protect this data has never been greater,” said Chad Spackman, president of CebaTech. “The GZIP family of CebaIP cores with AES cryptography is the perfect blend of high speed hardware-based compression technology to reduce the operational costs of storing and transmitting data, and to secure this data from potential enterprise-wide threats.” CebaTech expects the GZIP family to be attractive to companies building embedded networking and storage processors for a wide array of appliances, disk controllers, and storage backup systems.

The GZIP family is the first offering of CebaIP core configurations based on CebaTech’s CebaIP Platfrom. “Customers can choose from available GZIP configurations now, and grow with the platform over time to greater levels of integration and function, to meet the changing demands of their respective markets,” said Spackman.

Pricing and Availability

GZIP-based compression and decompression is available now for customer engagements, with general availability of the AES function in mid-2007.  Pricing for single use licenses start at $150,000. Future configurations of the CebaIP Platform that include partial TPC/IP, VLAN, link aggregation, and large send offload (LSO) will be released later in 2007.

About CebaTech

CebaTech uses its innovative C2R Compiler™, along with a comprehensive silicon development methodology, to realize complex data and storage networking functions in easy-to-integrate intellectual property (IP) cores. CebaTech is privately held. For more information about the company, CebaTech’s GZIP family of CebaIP Cores and the CebaIP Platform, visit www.cebatech.com.