Arteris Collaborates on Interposer Test Chip Projects With TSMC
Goal Is More Efficient and Timely Commercialization of Through-Silicon Via (TSV) Technology Using Arteris Network-on-Chip (NoC) Interconnect IP & Tool Products
SUNNYVALE, CA-- December 06, 2011 -- Arteris Inc., the inventor and leading supplier of network-on-chip (NoC) interconnect IP solutions, today announced that it is collaborating with TSMC by incorporating Arteris' FlexNoC Network-on-Chip (NoC) interconnect IP into an SoC die on silicon interposer test chip.
"TSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges," said Suk Lee, Director of Design Infrastructure Marketing at TSMC. "TSMC and Arteris are working together to make it easier for our joint customers to adopt these technologies."
In addition to working together on the interposer based test chip program, Arteris is a TSMC Open Innovation Platform Partner and a participant in TSMC's Reference Flows 11.0 and 12.0.
Unlike other interconnect solutions, Arteris's FlexNoC network on chip interconnect IP is physically implemented as a distributed network of small design elements within a SoC floorplan. Furthermore, FlexNoC's flexibility simultaneously addresses bandwidth, latency and quality of service (QoS) requirements introduced with wide data paths.
"TSMC and Arteris are working together to accelerate adoption of interconnect fabric technology by increasing design efficiency and proactively addressing the routing congestion and timing closure issues," said Charlie Janac, Arteris President and CEO.
About Arteris
Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster development of ICs, SoCs and FPGAs.
Founded by networking experts, Arteris operates globally with headquarters in Sunnyvale, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech. More information can be found at www.arteris.com.
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related News
- Sofics Tapes Out Test Chip on TSMC 4nm Process with Novel ESD IP and Low-Power 1.8V and 3.3V GPIO Solutions
- Reports Indicate TSMC to Tighten Scrutiny on Chinese AI Chip Clients; Potential Revenue Impact Between 5% to 8%
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
- Arteris Selected by Nextchip to Accelerate Chip Designs for Automotive Vision Technology
Latest News
- Arasan Announces immediate availability of its UFS 5.0 Host controller IP
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
- Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs