Disruption in library offering for the 90 nm LP process with Dolphin Integration's new generation of High Density Standard Cells
Meylan, France – February 18, 2011. The SESAME HD architecture of Standard Cells is the unexpected alternative to conventional 7 or 8-track libraries, for its cost and power reduction capabilities at major foundries in 90 nm LP process.
SESAME HD meets the requirements of high volume applications based on area-sensitive designs from high-density consumer and portable devices.
Highlights
Low die cost
- Up to 7% smaller area compared to conventional libraries
- 6-track high cells
- Only Metal 1 used for cell design
Up to 50% less leaky
- Multiple VT support
- Compliant with low power flow
Easy implementation
- Delivered with scripts for an automated optimization at each step of the implementation flow (optional)
- Custom PVT support
Optimal Design for Yield
- Design methodology ensuring High-Yield circuits despite Mismatch
- Specification of OCV margins
- Support for temperature inversion corners
Have a quick look at the Presentation Sheet
To request an access to the evaluation kit:
Registered users can get the Front End Package including technical documentation.
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/sesame
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related News
- Dolphin Integration announce the availability of the TSMC sponsored sROMet and DpRAM generators at 90 nm LP eFlash
- Standard Cells reducing leakage 40 to 60 times at 90 and 65 nm from Dolphin Integration
- Dolphin Integration unveils an sRAM architecture for Cost Sensitive Devices at 90 nm LP
- Dolphin Integration first to achieve 0.84 pA per bit in SpRAM at the 90 nm uLL embedded flash process
Latest News
- Cassia Proposes ‘Better Math’ for AI Efficiency
- QuickLogic Announces $1M eFPGA Hard IP Contract for Data Center ASIC
- Creonic Updates Doppler Channel IP Core with Extended Frequency Band and Sampling Range
- TSMC Price Hikes End the Era of Cheap Transistors
- Analogue Insight IP Group Launches Analogue Insight SAFE in Portland, Oregon to Deliver Certification-Grade Security IP for Next-Gen SoCs and Chiplets