PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP
T2M GmbH
•
HQ:
Unknown
PCIe Gen 3.1 transmission is supported by (PCIe 3.1) x4 PHY IP.
- TSMC
- 40nm
- LP
- In Production
Compare 8 PCIe Gen 3.1 IP Listing from 6 vendors
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Brite Semiconductor• HQ: China
YouPHY-Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstr…
- Video Processing
- Silicon Proven
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Truechip Solutions• HQ: USA
The PCIe Gen 7 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 7 interfa…
- PCI Express
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Truechip Solutions• HQ: USA
The PCIe Gen 6 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 6 interfa…
- PCI Express
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Truechip Solutions• HQ: USA
The USB4 Verification IP provides an effective & efficient way to verify the components interfacing with USB4 interface of an IP …
- USB
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Qbit labs• HQ: USA
PCIe Gen 6 controller IP
- PCI Express
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Synopsys, Inc.• HQ: USA
The USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF).
- Single-Protocol PHY
- Available on request
- Available
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Naneng Microelectronics• HQ: China
IP
- Single-Protocol PHY