The MIPI C-PHY IPis a high-frequency, low-power, low cost, physical layer.
- MIPI PHY
The MIPI C-PHY IPis a high-frequency, low-power, low cost, physical layer.
Physical interface for CSI-2 providing 5.7Gbps per lane of bandwidth The MIPI C-PHY V1.0 improves throughput over a bandwidth-lim…
MIPI CPHY Verification IP is compliant with MIPI CPHY specification and verifies CPHY devices.
MIPI CPHY v1.1 Analog Interface
The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5, N3)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.0 D-PHY v1.2 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…