IP
- MIPI PHY
- Silicon Proven
IP
MIPI D-PHY Rx IP, Silicon Proven in GF 55LP
Version 1.2 of the D-PHY specification is fully complied with by the MIPI D-PHY Analog RX IP Core.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
The D-PHY specification, version 1.2, is fully complied with by the MIPI D-PHY Analog RX IP Core.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
The MIPI D-PHY RX IP Core fully adheres to the D-PHY specification, version 1.2.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
Various manufacturing nodes using C-PHY/D-PHY Combo at minimal cost and power.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Rx IP Core in 28HPC+ aligns precisely with the D-PHY specification version 1.2, facilitating support for the Displ…
MIPI D-PHY Rx IP, Silicon Proven in SMIC 55LL
The D-PHY specification, version 1.2, is perfectly complied with by the MIPI D-PHY Analog RX IP Core.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP
The MIPI D-PHY Analog RX IP Core is fully compliant to the D-PHY specification version 1.2.
MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
The MIPI D-PHY Analog RX IP Core completely complies with the D-PHY specification, version 1.2.
The MIPI® D-PHY RX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
MIPI DPHY Rx 2 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Rx 4 Lanes - UMC 22ULP 1.8V, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 4 Lanes - TSMC7FF18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 2 Lanes - TSMC7FF18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 4 Lanes - TSMC6ff18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 2 Lanes - TSMC6ff18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 4 Lanes - TSMC40ULP25
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 2 Lanes - TSMC40ULP25
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 4 Lanes - TSMC12FFC18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…