Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
The Ethernet SerDes IP solutions address the performance, power, and area requirements of today’s mobile, consumer, and enterpris…
IP for Automotive Applications
M31 provides the variety IP types which meet ISO 26262 vehicle function safety requirements for the different applications in the…
Virtex-5 FPGA, Gen1 PCI Express The Xilinx Endpoint solution for Gen PCI Express® includes a PCI Express 1-lane, 4-lane, and 8-la…
Multiprotocol 10G PHY, TSMC N7 x2, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
Multiprotocol 10G PHY, TSMC 16FFC x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
Multiprotocol 10G PHY, SS 8LPU x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
MP10, USB 3.1/PCIe 3.0 PHY, GF 22FFDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G Multi-Protocol PHY, GF 22FDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
SerDes requirements for system-on-chip (SoC) designs are becoming increasingly demanding and must support increasing numbers of p…
7 Series Integrated Block for PCI Express (PCIe)
Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
7 Series Gen2 Integrated Block for PCI Express (PCIe)
Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)
Xilinx provides a Spartan-6 FPGA Integrated Endpoint solution for PCI Express® (PCIe) to configure the Spartan-6 FPGA Integrated …
Virtex-6 Integrated Block for PCI Express (PCIe)
Xilinx provides a Virtex-6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex-6 FPGA Integrated Block for PC…
Proven PHY IP for USB3.1 with supporting multi-protocol feature The ® IP for 10Gbps Multi-Protocol PHY simplifies the design proc…