AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP
AMBA AXI to AHB Bridge.
- Protocol Bridge
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP
AMBA AXI to AHB Bridge.
AHB system Peripheral IP, Interrupt controller, Soft IP
Interrupt controller with AHB interface.
AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP
AHB to AXI bridge.
DMA controller with AXI interface.
AHB system Peripheral IP, AHB - to - AHB Bridge, Soft IP
AHB to AHB bridge.
Two Port Register File Compiler IP, UMC 0.162um Logic process
UMC 0.162um Logic process synchronous Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.162um G2 process
UMC 0.162um GII Logic process synchronous high density Single Port Register File SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process high density, Low Power mini Single Port SRAM.
One Port Register File Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process synchronous high density Single Port Register File SRAM memory compiler.
ROM Compiler IP, UMC 0.162um eHV process
UMC 0.162um eHV process synchronous 1P2M Metal ROM memory compiler.
ROM Compiler IP, UMC 0.153um MS process
UMC 153nm Mixed-Mode/Logic process synchronous Via1 ROM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.153um MS process
UMC 153nm Mixed-Mode/Logic process synchronous high density Dual Port SRAM memory compiler.
SRAM/ROM Controller IP, SRAM/ROM Controller, Soft IP
Static memory controller with AXI interface.
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 3.00.
PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP
PCIe Gen2 x4 Lane Endpoint Controller.
Memory Controller IP, NAND Flash memory Host controller, Soft IP
NAND flash host controller with AHB interface, it supports SLC and MLC NAND flash.
AXI system Peripheral IP, AXI/APB host bridge, Soft IP
AXI/APB host bridge controller.
SATA Controller IP, SATA Gen-3, Soft IP
SATA Device Controller.
AXI Bus Controller IP, Bus Controller, Soft IP
Register Slice Controller with AXI bus interface.