SATA Host 6G Controller on Kintex 7
The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 …
- SATA Controller
- Good
- Now
- SATA 6G
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
SATA Host 6G Controller on Kintex 7
The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 …
CMOS Low Power Programmable Frequency Divider(50-2400 MHz) IP Fabricated
IP
900MHz, 2140MHz & 2700 MHz, 1 watt wide band Power Amplifier
IP
Synchronous FIFO with second read/write port as companion to A2_CAM_FIFO
Synchronous FIFO with second read/write port as companion to A2_CAM_FIFO
IP
10-bit dual-port 30MHz ~ 85MHz LVDS Tx;
IP
16-bit 48KSPS stereo Audio ADC;
IP
IP
IP
VeriSilicon UMC 0.18μm CF I/O
VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II lo…
IP
IP
GP Successive Approximation A/D
IP
2-ch 24-bit 192KSPS Audio DAC; TSMC 40nm LP
IP
10/100 Base-TX Fast Ethernet PHY; TSMC 55nm GP
IP
USB 2.0 OTG PHY IP, OTG, UMC 0.153um Logic process
USB OTG 2.0 PHY, UMC 0.153um Logic process.
Controller IP, SPI Flash controller, Soft IP
Flash Controller with SPI Interface.
AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP
L2 cache controller with AXI interface.
AXI system Peripheral IP, Interrupt Controller, Soft IP
Generic Interrupt Controller with AXI interface.
AXI system Peripheral IP, AXI to AXI Bridge, Soft IP
AMBA AXI to AXI Bridge.