Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
- UMC
- 250nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Specialty PCI IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 3.3V PCI IO cells.
Specialty PECL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process Low Voltage true 3.3V PECL IO cells.
Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 2.5V SSTL2 IO cells.
General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process
UMC 0.18um GII Logic process standard Multi-Voltage IO.
Linear Regulator IP, Output: 3.3V/240mA, UMC 0.18um LL process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process.
Voltage Detector IP, UMC 0.18um LL process
Voltage detector for flash protect, UMC 0.18um LL Logic process.
Voltage Detector IP, UMC 0.18um LL process
VDT for MMC, UMC 0.18um LL Logic process.
Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=23uA, UMC 0.18um LL Logic process.
Linear Regulator IP, Output: 3.3V/100mA, UMC 0.15um SP process
3.3V with 100mA driving capability, Istb=65uA Linear Regulator, UMC 0.15um SP Logic process.
Two Port Register File Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous Single Port Register File SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous high density Single Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
DDR2 SDRAM Controller
The host/device (OTG) solutions include a variety of host device configurations around a single USB port.
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec.