PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process
PCI-Express II PHY, UMC 90nm SP/RVT Low-K process.
- PCIe Gen2
- UMC
- 90nm
- SP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process
PCI-Express II PHY, UMC 90nm SP/RVT Low-K process.
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process
PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process.
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process.
Two Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous high density Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 65nm SP process
UMC 0.65um SP/RVT Low-K Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process synchronous high density Two Port Register File SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 90nm LL process
UMC 90nm Logic process low leakage devices synchronous Low Power Single Port hihg density memory compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm LL process
UMC 90nm LL/RVT Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy.
Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process
UMC 90nm SP/RVT Low-K Logic process Single Port SRAM (Introduce Redundancy feature to the existing FSD0A_B_SH).
Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process
UMC 90nm SP/ Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy.
One Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous Single Port SRAM.
Single Port SRAM Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process 1-port high density memory compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process synchronous high density, Single Port SRAM compiler with the row redundancy.
Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process
UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM with redundaycy memory compiler.
Single Port SRAM Compiler IP, UMC 65nm SP process
UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM memory compiler.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low_K Logic process synchronous high density One Port Register File compiler.