GSMC 0.18um 3.3v/1.8v 80mA power regulator
Present project is a regulator that generates 1.8v voltage from 3.3v power supply.
- LDO Voltage Regulator
- In Production
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
GSMC 0.18um 3.3v/1.8v 80mA power regulator
Present project is a regulator that generates 1.8v voltage from 3.3v power supply.
GSMC18_RCG_03 is to generate random code with the sampling clock up to 250MHz.
GSMC 0.18µm 5v-5v/3v/1.8v Power Regulator
This IP is a Low-Dropout (LDO) 5V to 5V/3V/1.8V power regulator in GSMC 0.18μm Logic/EFLASH process.
GSMC 0.18um 3.3V Power on Reset
The present Power-On-Reset circuit generates system reset pulses (RST) when the power supplier is from 1.62V to 3.6V.
GSMC 0.18μm 3.3v-1.8v Noise Current Source
GSMC18_NCS_01 is a Noise Current Source IP.
GSMC 0.18um 11Bit 500Ksps R2R DAC
GSMC18_R2RDAC_04 is a 11Bit 500KHz DAC IP.
This IP is specially designed for anti-tamper protection.
GSMC16RF process VPPIO, provides 6.5V power supply IO pads for OTP application.
VeriSilicon GSMC 0.16um RF 1.8V/3.3V VPPIO_DUP_01 IO library developed by VeriSilicon is optimized for Grace Semiconductor Manufa…
VCC Detector (VDT) circuit - voltage level of I/O (VIN) Detection
The present IP is a VCC Detector (VDT) circuit, which prevents the possibilities of causing Flash writing failure or internal ope…
GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM
Based on GSMC 0.13um 1.5V/12V eFlash process, current design of the IP detects light with photodiode.
GSMC 0.13um 5v-3.3v&1.5v Power Regulator
This IP is a Low-Dropout (LDO) 5V to 3.3V&1.5V power regulator in GSMC 0.13um low power 4P5M e-flash dual gate process.
GSMC 0.13um Low Power e-Flash 1.5V POR
This IP is a Power-On-Reset circuit, it detects the voltage level of POR_VDDC port, when VPOR_VDDC rises higher than the threshol…
This IP is a programmable Analog PLL suitable for high speed clock generation.
GSMC 0.13μm Low Power Process VCC Detector
This IP contains two Voltage Detector (VDT) circuits and a Power-On-Reset (POR) circuit.
GSMC 0.13μm Low Power Process 2.6~3.63v -> 1.5v Power Regulator
Targeted in GSMC 0.13μm Low Power 1.5V/3.3V 1P6M process, current design of Power Regulator is to provide 1.5v power supply which…
GSMC 0.13um Low Power Process Delay Cells
G13LPV33_DELAYRC_01 is to generate rise/fall delay ranging from 0.15ns to 5ns.
To provide a solution to MMC cards, SMIC18_MMC_07E_4IN1 is consolidated by four independent IPs: SMIC18_PRG_03E_33T18V60_160mA, S…
The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6…
The 10G/1G dual-mode Ethernet MAC offers an IEEE802.3-2008 (802.3ae) compliant solution that meets the requirements for 10Gbps LA…
The LDS SATA DEVICE STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA…