125M 9bit 2.5bit pipeline share-OP ADC for 10/100/1000 Ethernet DPHY use; UMC 28nm HPC/Low-K process
- 9 Bit
- UMC
- 28nm
- HPC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
125M 9bit 2.5bit pipeline share-OP ADC for 10/100/1000 Ethernet DPHY use; UMC 28nm HPC/Low-K process
A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process
A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process
Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process
Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)
12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS SAR A/D Converter; UMC 28 nm HPC process
10 bit 1MSPS SAR A/D Converter; UMC 28 nm HPC process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
UMC 55uLP ADC
Analog Comparator; 0.25um Logic process
Analog Comparator; 0.25um Logic process
HHGrace 0.11um ULL Process 6track Power Management Kit
HHGrace 0.11um Ultra Low Leakage 6track PMK Library
HHGrace 0.11um ULL Process 6track Std Cell Library
HHGrace 0.11um Ultra Low Leakage 6track Std Cell Library
HHGrace 0.11um Low Power Process 6track Power Management Kit
HHGrace 0.11um Low Power 6track PMK Library
HHGrace 0.11um Low Power Process 6track Std Cell Library
HHGrace 0.11um Low Power 6track Std Cell Library
VeriSilicon SMSB 0.18um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor …
HHGrace 0.11um ULL Multiple power supply IO library
Multiple power supply IO library for HHGrace 0.11um Eflash Ultra Low Leakage Dual Gate ( 1.5V/5V ) process