PLL IP Listing

Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process

• UMC
• 55nm
• ULP

This IP is a programmable Analog PLL suitable for high speed clock generation.

• PLL
• Pre-Silicon

This IP is a programmable Analog PLL suitable for high speed clock generation.

• GlobalFoundries
• 28nm
• SLP
• Pre-Silicon

This IP is a programmable Analog PLL suitable for high speed clock generation.

• GlobalFoundries
• 28nm
• SLP
• Silicon Proven

This IP is a programmable Analog PLL suitable for high speed clock generation.

• GlobalFoundries
• 22nm
• FDX
• Pre-Silicon

The GF40LPV25_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver ampli…

• Audio Codec
• Silicon proven

The GF28SLPV18_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver ampl…

• GlobalFoundries
• 28nm
• SLP
• Silicon Proven

IMEC’s divider-less All-Digital Phase Locked Loop (ADPLL) combines world’s lowest power consumption with performance and small si…

• TSMC
• 40nm
• G
• Silicon Proven

Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.

• UMC
• 28nm
• HPC+

This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synt…

• UMC
• 40nm
• LP

Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process

• UMC
• 55nm
• LP

Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.

• UMC
• 28nm
• HPC

Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process

• UMC
• 28nm
• HPC
• Pre-Silicon

Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process

• UMC
• 40nm
• Pre-Silicon

Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process

• UMC
• 28nm
• HPC

Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process

• UMC
• 40nm
• LP

Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process

• UMC
• 55nm

Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process

• UMC
• 28nm
• HPC
• Pre-Silicon

Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Enhancement) Logic Process

• UMC
• 110nm
• HS

Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process

• UMC
• 55nm
• LP
• Pre-Silicon