32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification.
- RISC-V
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification.
Provides pixel processing functions such as cropping, color space conversion (CSC), alpha blending, 3D LUT, and flexible resizing.
10-bit successive approximation Analog-to-Digital Converter (ADC) is designed for high-performance applications.
DisplayPort 1.2a TX PHY targeting 28nm Artix-7
DisplayPort 1.2a compatible AMD/Xilinx hardware specific Hardware proven on AMD/Xilinx 28nm FPGA fabric Fabric: 28nm Artix-7 Tran…
ASIL B Ready PCIe 5.0 Integrity and Data Encryption Security Module
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to …
VeriSyno offers a variety of digital IPs tailored to meet the demands of consumer, industrial, and automotive SoCs, enabling effi…
VeriSyno provides a flexible and configurable security IP solution, which includes common symmetric encryption algorithms, random…
112G VSR PHY, TSMC N5 x2, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
Gigabit Ethernet PHY
PCIe Gen4 RX/TX IP Supporingt PCIe 1.0/2.0/3.0/4.0 up to 16Gbps. CTLE boosts up to 18dB at 8GHz
Support PCIe 1.0/2.0/3.0/4.0 up to 16Gbps.
PCIe 5.0 PHY, SS SF5 x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
GEON™ Secure Boot Hardware Engine
GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or othe…
Video Super Resolution Accelerator IP
Engineered specifically for AI‑driven super‑resolution algorithms, delivering exceptional computational efficiency
Multipurpose Security Protocol Accelerator - Functional Safety ASIL B support
The Multipurpose Security Protocol Accelerator (SPAcc) offers designers unprecedented configurability to address the complex secu…
Neoverse Compute Subsystems N2 (CSS N2)
Neoverse CSS N2: The Arm Neoverse N2 Platform, Delivered to Partners as a Verified, Performance-Validated Customizable Subsystem …
A CPU Foundation for the AI-Driven Datacenter The Arm Neoverse V3 CPU is built to deliver maximum performance for cloud applicati…
Optimal Performance and Power Efficiency for Hyperscale, Telecom, Networking, and Infrastructure Edge Devices The Arm Neoverse N3…