LDO regulator on SMIC 40nm, 2.1v output
The present IP is a low dropout voltage regulator, which can support 360uA current load.
- SMIC
- 40nm
- Silicon Proven
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LDO regulator on SMIC 40nm, 2.1v output
The present IP is a low dropout voltage regulator, which can support 360uA current load.
The present IP is a voltage reference buffer, which is developed with SMIC 65nm ETOX Nor Flash process.
LDO regulator on SMIC 40nm, 1.13v output
The present IP is a low dropout voltage regulator, which can support 10uA DC current load.
LDO regulator on SMIC 40nm, 1.42v output
The present IP is a low dropout voltage regulator, which can support 10uA DC current load.
LDO regulator on SMIC 40nm, up to 12mA
The present IP is a low-dropout (LDO) voltage regulator supporting a 12mA load current with an input voltage range of 2.7V to 3.6…
Capless LDO regulator on SMIC 65nm
The present IP is a low-dropout (LDO) and capacitor-less voltage regulator developed using SMIC's 65nm ETOX Nor Flash process.
Integer-N PLL, 600M-2.4G on SMIC 40nm
This present IP is a self-biased Phase Locked Loop (PLL) circuit, which can cover 600MHz-2.4GHz vco output frequency.
Integer-N PLL, 32M ~ 256MHz on UMC 55nm
This present IP is a Phase Locked Loop (PLL) circuit.
Integer-N PLL, 800M-3.2G on TSMC 12nm
This present IP is a charge-pump Phase Locked Loop (PLL) circuit, which can cover 800MHz-3200MHz vco output frequency.
Comparator with configurable hysteresis input on UMC 55nm
This present IP is a comparator which is used to do the comparison between the different input groups, which operates in 3.3v pow…
Charge-Pump positive voltage generator with LDO in-built on SMIC 65nm
The present IP is a charge-pump and low dropout voltage generator, which is developed with SMIC 65nm ETOX Nor Flash process.
The present IP is a charge-pump voltage generator developed using SMIC's 65nm ETOX Nor Flash process.
The present IP is a charge-pump voltage generator developed using SMIC's 65nm ETOX Nor Flash process.
Low Power BandGap Reference with chopper on SMIC 40nm
The IP is a Band-gap reference generator circuit.
Low Power BandGap Reference on SMIC 65nm
The BGR IP is a BandGap reference circuit for low-power application which just consumes 3.2uA in operation which works well in 1.…
Low Power BandGap Reference on SMIC 40nm
The BGR IP is a BangGap Reference for low-power application.
PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.
DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM devi…
I²S Controller is designed to transfer audio data to and from Audio codec.