LPDDR4 multiPHY V2 - TSMC 22ULP
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
- Controller + PHY + 1
- LPDDR4
- TSMC
- 22nm
- ULP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
LPDDR4 multiPHY V2 - TSMC 22ULP
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY - TSMC 16FFC18 for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4 multiPHY V2 - GF 22FDX18 for Automotive, ASIL B Random, AEC-Q100 Grade 1
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY Plus - GF 12LP18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY Plus - GF 12LP+18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
High-performance and low-power 3D graphics IP core
High-performance and low-power 3D graphics IP core for embedded devices.
The AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, powe…
High-performance AI dataflow processor with scalable vector compute capabilities
The new XM Series offers an extremely scalable and efficient AI compute engine.
WiFi 6 Transceiver -1x1 single-band
IP
WiFi 6 Transceiver - 2x2 concurrent dual-band
IP
WiFi 6 transceiver IP - 1x1 concurrent dual-band
IP
High Speed Single Port Compiler on TSMC 40nm ULP
Single port SRAM compiler with low power retention mode Bit Cell Power Supply (V) 6T 1.1 Process Technology TSMC 40nm ULP Supply …
64x1 Bits OTP (One-Time Programmable) IP, TSMC 0.18um SiGe BiCMOS 1.8V/3.3V General Purpose Process
The ATO00064X1TS180SGE3NA is organized as a 64-bit by 1 one-time programmable (OTP).
128x16 Bits OTP (One-Time Programmable) IP, DBHitek 0.13um BCD Process Platforms
The ATO0128X16DB130BSA3NA is organized as a 128x16 one-time programmable (OTP).
256x1 Bits OTP (One-Time Programmable) IP, VIS 110 nm 1.2V/5.0V BCD Process
The AT256X1V110BCD0AA is organized as 256 bits by 1 one-time programmable in 1-bit read and 1-bit program modes.
16x8 Bits OTP (One-Time Programmable) IP, VIS 150nm 1.8V BCD Process
The ATO00016X8VI150BG22NA is organized as 16 bits by 8 one-time programmable in 8-bit read and 1-bit program modes.
4Kx8 Bits OTP (One-Time Programmable) IP, VIS 0.15µm 1.8V/6V SOI BCD EPI Process
The ATO0004KX8VI150SOI3XX00A is organized as a 4K-bits by 8 one-time programmable.
16x8 Bits OTP (One-Time Programmable) IP, TSMC CM018G 0.18um 1.8V/3.3V Process
The ATO00016X8TS180CMG3NA is organized as 16 bits by 8 one-time programmable (OTP) in 8-bit read and 1-bit program modes.