PLL IP Listing

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Compare 3,564 PLL IP Listing from 105 vendors

  • DDR3/2 PHY

    VeriSyno Microelectronics Co., Ltd.
    HQ: The People's Republic of China

    The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…

    • Controller + PHY + 1
    • DDR3
    Maturity: Production
  • XAUI PHY

    VeriSyno Microelectronics Co., Ltd.
    HQ: The People's Republic of China

    The XAUI PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI …

    • Single-Protocol PHY
    • Silicon Proven
    • Immediate
    Maturity: Production
  • SATA 6G PHY

    VeriSyno Microelectronics Co., Ltd.
    HQ: The People's Republic of China

    The SATA 6G PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SA…

    • Single-Protocol PHY
    • Silicon Proven
    • Immediate
    Maturity: Production
  • PCIe Gen2 PHY

    VeriSyno Microelectronics Co., Ltd.
    HQ: The People's Republic of China

    The PCIe2 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI …

    • Single-Protocol PHY
    • Silicon Proven; Design Ready(SMIC,28)
    • Immediate
    Maturity: Production
  • PCIe Gen1 PHY

    VeriSyno Microelectronics Co., Ltd.
    HQ: The People's Republic of China

    The PCIe1 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into comp…

    • Single-Protocol PHY
    • Silicon Proven
    • Immediate
    Maturity: Production
  • USB 3.0 PHY

    VeriSyno Microelectronics Co., Ltd.
    HQ: The People's Republic of China

    The USB 3.0 PHY is a , mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into …

    • USB 3.0
    Maturity: Production
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