3.3V Power Support I/O Pad Set
The 3.3V Support: Power library provides a full complement of cells to support the assembly of a pad ring by abutment.
- TSMC
- 7nm
- N7+
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
3.3V Power Support I/O Pad Set
The 3.3V Support: Power library provides a full complement of cells to support the assembly of a pad ring by abutment.
3.3V 100 MHz Oscillator I/O Pad Set
The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
1.8V Programmable 100MHz Oscillator I/O Pad Set
The Oscillators library provides a programmable oscillator for on-chip asynchronous clock generation with an appropriate external…
1.8V Power Support I/O Pad Set
The 1.8V Support: Power library provides a full complement of cells to support the assembly of a pad ring by abutment.
Neural network processor designed for edge devices
Kneron NPU IP Series are neural network processors that have been designed for edge devices.
General Video Interface HS Receiver PHY
IP
General Video Interface HS Transmitter PHY
IP
Devices from Telematics family provide a cost effective microprocessor solution for automotive telematics applications based on a…
AHB Single Channel DMA Controller
The AHB Single Channel DMA Controller core is a configurable single channel direct memory access controller.
DPU for Convolutional Neural Network
The Xilinx® Deep Learning Processor Unit (DPU) is a programmable engine dedicated for convolutional neural network.
VCO3, Fcenter 12GHz - GlobalFoundries 40nm
VCO3, Fcenter 12GHz - GlobalFoundries 40nm
VCO2, High-Q, Fcenter=7.2GHz - GlobalFoundries 55nm
VCO2, High-Q, Fcenter=7.2GHz - GlobalFoundries 55nm
VCO2, Fcenter 10GHz - GlobalFoundries 40nm
VCO2, Fcenter 10GHz - GlobalFoundries 40nm
VCO1, Wide-Tuning, Fcenter=6GHz - GlobalFoundries 55nm
VCO1, Wide-Tuning, Fcenter=6GHz - GlobalFoundries 55nm
VCO1, Fcenter 7GHz - GlobalFoundries 40nm
VCO1, Fcenter 7GHz - GlobalFoundries 40nm
Temperature Sensor, voltage output - XFAB 180nm
Temperature Sensor, voltage output - XFAB 180nm
Temperature Sensor, voltage output - GlobalFoundries 40nm
Temperature Sensor, voltage output - GlobalFoundries 40nm
Transimpedance Amplifier, BW=50MHz - GlobalFoundries 22nm
Transimpedance Amplifier, BW=50MHz - GlobalFoundries 22nm
Synchronizer, up to 6GHz - GlobalFoundries 55nm
Synchronizer, up to 6GHz - GlobalFoundries 55nm
Synchronizer, up to 12GHz - GlobalFoundries 40nm
Synchronizer, up to 12GHz - GlobalFoundries 40nm