Vendor: True Circuits, Inc. Category: DLL

UMC L110SP 110nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…

Overview

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay line which rejects temperature and supply voltage variations, and has high supply noise rejection for very low jitter operation.

TCI can configure this block to have almost any number of slaves (which delay the arbitrary signals) with a single master section (which establishes the time base) to minimize area and power. The slave delays can be independently set to precise values or dynamically adjusted after determining the boundaries of a data eye. The DDR DLL has excellent linearity and very high resolution.

TCI can also configure this block to output multi-phase clocks directly from the reference clock.

Key features

  • Designed for high-speed DDR style interface applications.
  • Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
  • Delays multiple periodic or aperiodic signals independent of voltage and temperature.
  • Delivers optimal jitter performance over a wide frequency range.
  • Available in flexible form factors for easier integration.

What’s Included?

  • GDSII (100% DRC and LVS clean)
  • LVS Spice netlist
  • Verilog model
  • Synopsys synthesis model
  • LEF for clock generator PLL
  • User Guidelines including:
    • integration guidelines,
    • layout guidelines,
    • testability guidelines,
    • packaging guidelines,
    • board-level guidelines

Silicon Options

Foundry Node Process Maturity
UMC 110nm 110nm 1100 nm

Specifications

Identity

Part Number
TCI-U11SP-DDRHDLL
Vendor
True Circuits, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about DLL IP cores

What is UMC L110SP 110nm DDR DLL - 76MHz-380MHz?

UMC L110SP 110nm DDR DLL - 76MHz-380MHz is a DLL IP core from True Circuits, Inc. listed on Semi IP Hub. It is listed with support for umc.

How should engineers evaluate this DLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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