Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
Global UniChip Corp. (GUC)
Category:
SRAM
TSMC CLN5FF High Density Single Port SRAM Compiler
IGMSHDY01A is a synchronous ULVT / LVT periphery high density single port SRAM compiler.
Overview
IGMSHDY01A is a synchronous ULVT / LVT periphery high density single port SRAM compiler. It is developed with TSMC 5 nm 0.75 V/1.2 V CMOS LOGIC FinFET Compact Process. Different combinations of words, bits, and column-selected number (MUX) could be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMSHDY01A compiler is capable of providing suitable synchronous SRAM instances models within minutes. It is capable of automatically generating the datasheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as setup/hold time and minimum high/low pulse width requirements are satisfied. This allows a more flexible clock falling edge during each operation.
Given the desired size and timing constraints, the IGMSHDY01A compiler is capable of providing suitable synchronous SRAM instances models within minutes. It is capable of automatically generating the datasheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as setup/hold time and minimum high/low pulse width requirements are satisfied. This allows a more flexible clock falling edge during each operation.
Key features
- The High Density Single Port SRAM operates within voltage range from 0.675 V to 0.825 V and junction temperature range from -40 °C to 125 °C. The available supported macro size is configurable from 512 bits to 576K bits. The Compiler is divided into 1 groups according to their column selection numbers (Mux=8).
- ? Pins and metal layers
- – 1P3M (1X_h_1Xb_v): 3 metal layers used and top metal is MXb.
- – Power mesh supported with M3 pins
- ? Compilation options
- – MUX selection for the desired macro aspect ratio
- – Bit-write mask function (BWEB pin) that allows writing to designated bits in a word
- ? Power management
- – Sleep mode powers down most of the peripheral circuits for leakage reduction with data retention.
- – Deep sleep mode powers down most of the peripheral circuits for leakage reduction and retains memory array content with lower voltage.
- – Shutdown mode achieves highest leakage reduction without data retention.
- ? General features
- – High Current TSMC 6T 0.0257 um2 SRAM bit cell
- – Frequently used EDA model support
- – Column redundancy
- – Dual rail design to support Dynamic Voltage Frequency Scaling (DVFS) application
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 5nm | N5FF | Available on request |
Specifications
Identity
Part Number
IGMSHDY01A
Vendor
Global UniChip Corp. (GUC)
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan
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Frequently asked questions about SRAM IP cores
What is TSMC CLN5FF High Density Single Port SRAM Compiler?
TSMC CLN5FF High Density Single Port SRAM Compiler is a SRAM IP core from Global UniChip Corp. (GUC) listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.